/dts-v1/; /* node '/' defined in zephyr\dts\common\skeleton.dtsi:9 */ / { #address-cells = < 0x1 >; /* in zephyr\dts\common\skeleton.dtsi:10 */ #size-cells = < 0x1 >; /* in zephyr\dts\common\skeleton.dtsi:11 */ model = "EWS STM32G0B1KBU6 board"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:13 */ compatible = "st,stm32g0b1kb-ews"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:14 */ /* node '/chosen' defined in zephyr\dts\common\skeleton.dtsi:13 */ chosen { zephyr,flash-controller = &flash; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:28 */ zephyr,console = &usart1; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:17 */ zephyr,shell-uart = &usart1; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:18 */ zephyr,uart-mcumgr = &usart1; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:19 */ zephyr,sram = &sram0; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:20 */ zephyr,flash = &flash0; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:21 */ zephyr,code-partition = &slot0_partition; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:22 */ zephyr,canbus = &fdcan2; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:23 */ }; /* node '/aliases' defined in zephyr\dts\common\skeleton.dtsi:15 */ aliases { led0 = &status_led; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:49 */ pfet0 = &pfet1; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:50 */ pfet1 = &pfet2; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:51 */ watchdog0 = &iwdg; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:52 */ die-temp0 = &die_temp; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:53 */ volt-sensor0 = &vref; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:54 */ volt-sensor1 = &vbat; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:55 */ }; /* node '/soc' defined in zephyr\dts\arm\armv6-m.dtsi:6 */ soc { #address-cells = < 0x1 >; /* in zephyr\dts\arm\armv6-m.dtsi:7 */ #size-cells = < 0x1 >; /* in zephyr\dts\arm\armv6-m.dtsi:8 */ interrupt-parent = < &nvic >; /* in zephyr\dts\arm\armv6-m.dtsi:10 */ ranges; /* in zephyr\dts\arm\armv6-m.dtsi:11 */ compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:23 */ /* node '/soc/interrupt-controller@e000e100' defined in zephyr\dts\arm\armv6-m.dtsi:13 */ nvic: interrupt-controller@e000e100 { #address-cells = < 0x1 >; /* in zephyr\dts\arm\armv6-m.dtsi:14 */ compatible = "arm,v6m-nvic"; /* in zephyr\dts\arm\armv6-m.dtsi:15 */ reg = < 0xe000e100 0xc00 >; /* in zephyr\dts\arm\armv6-m.dtsi:16 */ interrupt-controller; /* in zephyr\dts\arm\armv6-m.dtsi:17 */ #interrupt-cells = < 0x2 >; /* in zephyr\dts\arm\armv6-m.dtsi:18 */ arm,num-irq-priority-bits = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:575 */ phandle = < 0x1 >; /* in zephyr\dts\arm\armv6-m.dtsi:10 */ }; /* node '/soc/timer@e000e010' defined in zephyr\dts\arm\armv6-m.dtsi:21 */ systick: timer@e000e010 { compatible = "arm,armv6m-systick"; /* in zephyr\dts\arm\armv6-m.dtsi:22 */ reg = < 0xe000e010 0x10 >; /* in zephyr\dts\arm\armv6-m.dtsi:23 */ }; /* node '/soc/flash-controller@40022000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:114 */ flash: flash-controller@40022000 { compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:115 */ reg = < 0x40022000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:116 */ interrupts = < 0x3 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:117 */ clocks = < &rcc 0x38 0x100 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:118 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:120 */ #size-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:121 */ /* node '/soc/flash-controller@40022000/flash@8000000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:123 */ flash0: flash@8000000 { compatible = "st,stm32-nv-flash", "soc-nv-flash"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:124 */ write-block-size = < 0x8 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:126 */ erase-block-size = < 0x800 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:127 */ max-erase-time = < 0x28 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:129 */ reg = < 0x8000000 0x80000 >; /* in zephyr\dts\arm\st\g0\stm32g0b1Xe.dtsi:17 */ /* node '/soc/flash-controller@40022000/flash@8000000/partitions' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:133 */ partitions { compatible = "fixed-partitions"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:134 */ #address-cells = < 0x1 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:135 */ #size-cells = < 0x1 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:136 */ /* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@0' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:138 */ boot_partition: partition@0 { label = "mcuboot"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:139 */ reg = < 0x0 0x4000 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:140 */ read-only; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:141 */ }; /* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@4000' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:144 */ slot0_partition: partition@4000 { label = "image-0"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:145 */ reg = < 0x4000 0x18000 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:146 */ }; /* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@1c000' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:149 */ slot1_partition: partition@1c000 { label = "image-1"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:150 */ reg = < 0x1c000 0x4000 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:151 */ }; }; }; }; /* node '/soc/rcc@40021000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:133 */ rcc: rcc@40021000 { compatible = "st,stm32f0-rcc"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:134 */ #clock-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:135 */ reg = < 0x40021000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:136 */ clocks = < &pll >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:83 */ clock-frequency = < 0x3d09000 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:84 */ ahb-prescaler = < 0x1 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:85 */ apb1-prescaler = < 0x1 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:86 */ phandle = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:118 */ /* node '/soc/rcc@40021000/reset-controller' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:138 */ rctl: reset-controller { compatible = "st,stm32-rcc-rctl"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:139 */ #reset-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:140 */ phandle = < 0x4 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:245 */ }; }; /* node '/soc/interrupt-controller@40021800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:144 */ exti: interrupt-controller@40021800 { compatible = "st,stm32g0-exti", "st,stm32-exti"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:145 */ interrupt-controller; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:146 */ #interrupt-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:147 */ #address-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:148 */ reg = < 0x40021800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:149 */ clocks = < &rcc 0x40 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:150 */ interrupts = < 0x5 0x0 >, < 0x6 0x0 >, < 0x7 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:152 */ interrupt-names = "line0-1", "line2-3", "line4-15"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:153 */ line-ranges = < 0x0 0x2 >, < 0x2 0x2 >, < 0x4 0xc >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:154 */ num-lines = < 0x40 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:183 */ }; /* node '/soc/pin-controller@50000000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:157 */ pinctrl: pin-controller@50000000 { compatible = "st,stm32-pinctrl"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:158 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:159 */ #size-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:160 */ reg = < 0x50000000 0x2000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:161 */ /* node '/soc/pin-controller@50000000/gpio@50000000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:163 */ gpioa: gpio@50000000 { compatible = "st,stm32-gpio"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:164 */ gpio-controller; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:165 */ #gpio-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:166 */ reg = < 0x50000000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:167 */ clocks = < &rcc 0x34 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:168 */ phandle = < 0x7 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:503 */ }; /* node '/soc/pin-controller@50000000/gpio@50000400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:171 */ gpiob: gpio@50000400 { compatible = "st,stm32-gpio"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:172 */ gpio-controller; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:173 */ #gpio-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:174 */ reg = < 0x50000400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:175 */ clocks = < &rcc 0x34 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:176 */ phandle = < 0x9 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:526 */ }; /* node '/soc/pin-controller@50000000/gpio@50000800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:179 */ gpioc: gpio@50000800 { compatible = "st,stm32-gpio"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:180 */ gpio-controller; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:181 */ #gpio-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:182 */ reg = < 0x50000800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:183 */ clocks = < &rcc 0x34 0x4 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:184 */ phandle = < 0x8 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:508 */ }; /* node '/soc/pin-controller@50000000/gpio@50000c00' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:187 */ gpiod: gpio@50000c00 { compatible = "st,stm32-gpio"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:188 */ gpio-controller; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:189 */ #gpio-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:190 */ reg = < 0x50000c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:191 */ clocks = < &rcc 0x34 0x8 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:192 */ }; /* node '/soc/pin-controller@50000000/gpio@50001400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:195 */ gpiof: gpio@50001400 { compatible = "st,stm32-gpio"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:196 */ gpio-controller; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:197 */ #gpio-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:198 */ reg = < 0x50001400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:199 */ clocks = < &rcc 0x34 0x20 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:200 */ }; /* node '/soc/pin-controller@50000000/gpio@50001000' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:26 */ gpioe: gpio@50001000 { compatible = "st,stm32-gpio"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:27 */ gpio-controller; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:28 */ #gpio-cells = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:29 */ reg = < 0x50001000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:30 */ clocks = < &rcc 0x34 0x10 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:31 */ phandle = < 0xa >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:163 */ }; /* node '/soc/pin-controller@50000000/fdcan2_rx_pb0' defined in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:469 */ fdcan2_rx_pb0: fdcan2_rx_pb0 { pinmux = < 0x203 >; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:470 */ phandle = < 0xb >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:115 */ }; /* node '/soc/pin-controller@50000000/fdcan2_tx_pb1' defined in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:503 */ fdcan2_tx_pb1: fdcan2_tx_pb1 { pinmux = < 0x223 >; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:504 */ phandle = < 0xc >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:115 */ }; /* node '/soc/pin-controller@50000000/usart1_rx_pc5' defined in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:1744 */ usart1_rx_pc5: usart1_rx_pc5 { pinmux = < 0x4a1 >; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:1745 */ phandle = < 0x6 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:96 */ }; /* node '/soc/pin-controller@50000000/usart1_tx_pc4' defined in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:1859 */ usart1_tx_pc4: usart1_tx_pc4 { pinmux = < 0x481 >; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:1860 */ bias-pull-up; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:1861 */ phandle = < 0x5 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:96 */ }; /* node '/soc/pin-controller@50000000/usb_dm_pa11' defined in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:2008 */ usb_dm_pa11: usb_dm_pa11 { pinmux = < 0x170 >; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:2009 */ phandle = < 0xe >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:90 */ }; /* node '/soc/pin-controller@50000000/usb_dp_pa12' defined in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:2012 */ usb_dp_pa12: usb_dp_pa12 { pinmux = < 0x190 >; /* in modules\hal\stm32\dts\st\g0\stm32g0b1r(b-c-e)tx-pinctrl.dtsi:2013 */ phandle = < 0xf >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:90 */ }; }; /* node '/soc/rtc@40002800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:204 */ rtc: rtc@40002800 { compatible = "st,stm32-rtc"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:205 */ reg = < 0x40002800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:206 */ interrupts = < 0x2 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:207 */ prescaler = < 0x8000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:209 */ alarms-count = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:210 */ alrm-exti-line = < 0x13 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:211 */ clocks = < &rcc 0x3c 0x400 >, < &rcc 0x3 0x228005c >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:103 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:105 */ /* node '/soc/rtc@40002800/backup_regs' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:220 */ bbram: backup_regs { compatible = "st,stm32-bbram"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:221 */ st,backup-regs = < 0x5 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:222 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:223 */ }; }; /* node '/soc/watchdog@40003000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:227 */ iwdg: watchdog@40003000 { compatible = "st,stm32-watchdog"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:228 */ reg = < 0x40003000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:229 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:109 */ }; /* node '/soc/watchdog@40002c00' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:233 */ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:234 */ reg = < 0x40002c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:235 */ clocks = < &rcc 0x3c 0x800 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:236 */ interrupts = < 0x0 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:237 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:238 */ }; /* node '/soc/serial@40013800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:241 */ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:242 */ reg = < 0x40013800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:243 */ clocks = < &rcc 0x40 0x4000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:244 */ resets = < &rctl 0x60e >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:245 */ interrupts = < 0x1b 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:246 */ pinctrl-0 = < &usart1_tx_pc4 &usart1_rx_pc5 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:96 */ pinctrl-names = "default"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:97 */ current-speed = < 0x1c200 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:98 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:99 */ }; /* node '/soc/serial@40004400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:250 */ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:251 */ reg = < 0x40004400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:252 */ clocks = < &rcc 0x3c 0x20000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:253 */ resets = < &rctl 0x591 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:254 */ interrupts = < 0x1c 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:255 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:256 */ }; /* node '/soc/timers@40007c00' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:259 */ lptim1: stm32_lp_tick_source: timers@40007c00 { compatible = "st,stm32-lptim"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:260 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:262 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:263 */ reg = < 0x40007c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:264 */ interrupts = < 0x11 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:265 */ interrupt-names = "wakeup"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:266 */ clocks = < &rcc 0x3c 0x80000000 >, < &rcc 0x3 0x1320054 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:157 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:159 */ }; /* node '/soc/timers@40012c00' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:270 */ timers1: timers@40012c00 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:271 */ reg = < 0x40012c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:272 */ resets = < &rctl 0x60b >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:275 */ interrupts = < 0xd 0x0 >, < 0xe 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:276 */ interrupt-names = "brk_up_trg_com", "cc"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:277 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:278 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:279 */ clocks = < &rcc 0x40 0x800 >, < &rcc 0x9 0x160054 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:25 */ /* node '/soc/timers@40012c00/pwm' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:281 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:282 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:283 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:284 */ }; /* node '/soc/timers@40012c00/counter' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:287 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:288 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:289 */ }; /* node '/soc/timers@40012c00/qdec' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:292 */ qdec { compatible = "st,stm32-qdec"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:293 */ st,input-filter-level = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:294 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:295 */ }; }; /* node '/soc/timers@40000400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:299 */ timers3: timers@40000400 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:300 */ reg = < 0x40000400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:301 */ clocks = < &rcc 0x3c 0x2 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:302 */ resets = < &rctl 0x581 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:304 */ interrupts = < 0x10 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:305 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:306 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:307 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:308 */ /* node '/soc/timers@40000400/pwm' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:310 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:311 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:312 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:313 */ }; /* node '/soc/timers@40000400/counter' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:316 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:317 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:318 */ }; /* node '/soc/timers@40000400/qdec' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:321 */ qdec { compatible = "st,stm32-qdec"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:322 */ st,input-filter-level = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:323 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:324 */ }; }; /* node '/soc/timers@40002000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:328 */ timers14: timers@40002000 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:329 */ reg = < 0x40002000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:330 */ clocks = < &rcc 0x40 0x8000 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:331 */ resets = < &rctl 0x60f >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:333 */ interrupts = < 0x13 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:334 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:335 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:336 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:337 */ /* node '/soc/timers@40002000/pwm' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:339 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:340 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:341 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:342 */ }; /* node '/soc/timers@40002000/counter' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:345 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:346 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:347 */ }; }; /* node '/soc/timers@40014400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:351 */ timers16: timers@40014400 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:352 */ reg = < 0x40014400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:353 */ clocks = < &rcc 0x40 0x20000 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:354 */ resets = < &rctl 0x611 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:356 */ interrupts = < 0x15 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:357 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:358 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:359 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:360 */ /* node '/soc/timers@40014400/pwm' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:362 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:363 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:364 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:365 */ }; /* node '/soc/timers@40014400/counter' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:368 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:369 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:370 */ }; }; /* node '/soc/timers@40014800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:374 */ timers17: timers@40014800 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:375 */ reg = < 0x40014800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:376 */ clocks = < &rcc 0x40 0x40000 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:377 */ resets = < &rctl 0x612 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:379 */ interrupts = < 0x16 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:380 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:381 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:382 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:383 */ /* node '/soc/timers@40014800/pwm' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:385 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:386 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:387 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:388 */ }; /* node '/soc/timers@40014800/counter' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:391 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:392 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:393 */ }; }; /* node '/soc/i2c@40005400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:397 */ i2c1: i2c@40005400 { compatible = "st,stm32-i2c-v2"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:398 */ clock-frequency = < 0x186a0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:399 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:400 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:401 */ reg = < 0x40005400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:402 */ clocks = < &rcc 0x3c 0x200000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:403 */ interrupts = < 0x17 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:404 */ interrupt-names = "combined"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:405 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:406 */ phandle = < 0x14 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:561 */ }; /* node '/soc/i2c@40005800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:409 */ i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v2"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:410 */ clock-frequency = < 0x186a0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:411 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:412 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:413 */ reg = < 0x40005800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:414 */ clocks = < &rcc 0x3c 0x400000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:415 */ interrupts = < 0x18 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:416 */ interrupt-names = "combined"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:417 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:418 */ phandle = < 0x15 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:569 */ }; /* node '/soc/spi@40013000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:421 */ spi1: spi@40013000 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:422 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:423 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:424 */ reg = < 0x40013000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:425 */ clocks = < &rcc 0x40 0x1000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:426 */ interrupts = < 0x19 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:427 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:428 */ }; /* node '/soc/spi@40003800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:431 */ spi2: spi@40003800 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:432 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:433 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:434 */ reg = < 0x40003800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:435 */ clocks = < &rcc 0x3c 0x4000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:436 */ interrupts = < 0x1a 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:437 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:438 */ }; /* node '/soc/adc@40012400' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:441 */ adc1: adc@40012400 { compatible = "st,stm32-adc"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:442 */ reg = < 0x40012400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:443 */ clocks = < &rcc 0x40 0x100000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:444 */ clock-names = "adcx"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:445 */ interrupts = < 0xc 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:446 */ #io-channel-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:447 */ resolutions = < 0x60630c 0x51630c 0x42630c 0x33630c >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:448 */ sampling-times = < 0x3 0x5 0x8 0xd 0x14 0x28 0x50 0xa1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:458 */ num-sampling-time-common-channels = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:459 */ st,adc-sequencer = "fixed"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:460 */ st,adc-oversampler = "minimal"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:461 */ st,adc-internal-regulator = "startup-sw-delay"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:462 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:463 */ phandle = < 0x13 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:538 */ }; /* node '/soc/dma@40020000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:466 */ dma1: dma@40020000 { compatible = "st,stm32-dma-v2"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:467 */ #dma-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:468 */ reg = < 0x40020000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:469 */ clocks = < &rcc 0x38 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:471 */ dma-offset = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:473 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:474 */ interrupts = < 0x9 0x0 0xa 0x0 0xa 0x0 0xb 0x0 0xb 0x0 0xb 0x0 0xb 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:78 */ dma-requests = < 0x7 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:79 */ }; /* node '/soc/dmamux@40020800' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:478 */ dmamux1: dmamux@40020800 { compatible = "st,stm32-dmamux"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:479 */ #dma-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:480 */ reg = < 0x40020800 0x800 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:481 */ interrupts = < 0xb 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:482 */ dma-generators = < 0x4 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:484 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:486 */ dma-channels = < 0xc >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:142 */ dma-requests = < 0x49 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:143 */ }; /* node '/soc/power@40007000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:489 */ pwr: power@40007000 { compatible = "st,stm32-pwr"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:490 */ reg = < 0x40007000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:491 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:492 */ wkup-pins-nb = < 0x6 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:494 */ wkup-pins-pol; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:495 */ wkup-pins-pupd; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:496 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:498 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:499 */ /* node '/soc/power@40007000/wkup-pin@1' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:501 */ wkup-pin@1 { reg = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:502 */ wkup-gpios = < &gpioa 0x0 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:503 */ }; /* node '/soc/power@40007000/wkup-pin@2' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:506 */ wkup-pin@2 { reg = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:507 */ wkup-gpios = < &gpioa 0x4 0x1 >, < &gpioc 0xd 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:508 */ }; /* node '/soc/power@40007000/wkup-pin@4' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:514 */ wkup-pin@4 { reg = < 0x4 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:515 */ wkup-gpios = < &gpioa 0x2 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:516 */ }; /* node '/soc/power@40007000/wkup-pin@5' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:519 */ wkup-pin@5 { reg = < 0x5 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:520 */ wkup-gpios = < &gpioc 0x5 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:521 */ }; /* node '/soc/power@40007000/wkup-pin@6' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:524 */ wkup-pin@6 { reg = < 0x6 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:525 */ wkup-gpios = < &gpiob 0x5 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:526 */ }; /* node '/soc/power@40007000/wkup-pin@3' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:161 */ wkup-pin@3 { reg = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:162 */ wkup-gpios = < &gpioe 0x6 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:163 */ }; }; /* node '/soc/serial@40008000' defined in zephyr\dts\arm\st\g0\stm32g031.dtsi:15 */ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:16 */ reg = < 0x40008000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:17 */ clocks = < &rcc 0x3c 0x100000 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:18 */ resets = < &rctl 0x594 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:19 */ interrupts = < 0x1d 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:20 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:21 */ }; /* node '/soc/timers@40000000' defined in zephyr\dts\arm\st\g0\stm32g031.dtsi:29 */ timers2: timers@40000000 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:30 */ reg = < 0x40000000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:31 */ clocks = < &rcc 0x3c 0x1 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:32 */ resets = < &rctl 0x580 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:34 */ interrupts = < 0xf 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:35 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:36 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:37 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:38 */ /* node '/soc/timers@40000000/pwm' defined in zephyr\dts\arm\st\g0\stm32g031.dtsi:40 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:41 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:42 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:43 */ }; /* node '/soc/timers@40000000/qdec' defined in zephyr\dts\arm\st\g0\stm32g031.dtsi:46 */ qdec { compatible = "st,stm32-qdec"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:47 */ st,input-filter-level = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:48 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g031.dtsi:49 */ }; }; /* node '/soc/timers@40001000' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:13 */ timers6: timers@40001000 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:14 */ reg = < 0x40001000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:15 */ clocks = < &rcc 0x3c 0x10 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:16 */ resets = < &rctl 0x584 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:18 */ interrupts = < 0x11 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:19 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:20 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:21 */ /* node '/soc/timers@40001000/counter' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:23 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:24 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:25 */ }; }; /* node '/soc/timers@40001400' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:29 */ timers7: timers@40001400 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:30 */ reg = < 0x40001400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:31 */ clocks = < &rcc 0x3c 0x20 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:32 */ resets = < &rctl 0x585 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:34 */ interrupts = < 0x12 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:35 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:36 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:37 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:38 */ /* node '/soc/timers@40001400/counter' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:40 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:41 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:42 */ }; }; /* node '/soc/timers@40014000' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:46 */ timers15: timers@40014000 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:47 */ reg = < 0x40014000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:48 */ clocks = < &rcc 0x40 0x10000 >, < &rcc 0x9 0x180054 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:49 */ resets = < &rctl 0x610 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:51 */ interrupts = < 0x14 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:52 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:53 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:54 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:55 */ /* node '/soc/timers@40014000/pwm' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:57 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:58 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:59 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:60 */ }; /* node '/soc/timers@40014000/counter' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:63 */ counter { compatible = "st,stm32-counter"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:64 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:65 */ }; }; /* node '/soc/dac@40007400' defined in zephyr\dts\arm\st\g0\stm32g051.dtsi:69 */ dac1: dac@40007400 { compatible = "st,stm32-dac"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:70 */ reg = < 0x40007400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:71 */ clocks = < &rcc 0x3c 0x20000000 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:72 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:73 */ #io-channel-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g051.dtsi:74 */ }; /* node '/soc/serial@40004800' defined in zephyr\dts\arm\st\g0\stm32g071.dtsi:15 */ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:16 */ reg = < 0x40004800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:17 */ clocks = < &rcc 0x3c 0x40000 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:18 */ resets = < &rctl 0x592 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:19 */ interrupts = < 0x1d 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:20 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:21 */ }; /* node '/soc/serial@40004c00' defined in zephyr\dts\arm\st\g0\stm32g071.dtsi:24 */ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:25 */ reg = < 0x40004c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:26 */ clocks = < &rcc 0x3c 0x80000 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:27 */ resets = < &rctl 0x593 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:28 */ interrupts = < 0x1d 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:29 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:30 */ }; /* node '/soc/ucpd@4000a000' defined in zephyr\dts\arm\st\g0\stm32g071.dtsi:37 */ ucpd1: ucpd@4000a000 { compatible = "st,stm32-ucpd"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:38 */ reg = < 0x4000a000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:39 */ clocks = < &rcc 0x3c 0x2000000 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:40 */ interrupts = < 0x8 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:41 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:42 */ }; /* node '/soc/ucpd@4000a400' defined in zephyr\dts\arm\st\g0\stm32g071.dtsi:45 */ ucpd2: ucpd@4000a400 { compatible = "st,stm32-ucpd"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:46 */ reg = < 0x4000a400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:47 */ clocks = < &rcc 0x3c 0x4000000 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:48 */ interrupts = < 0x8 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:49 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g071.dtsi:50 */ }; /* node '/soc/can@40006400' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:35 */ fdcan1: can@40006400 { compatible = "st,stm32-fdcan"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:36 */ reg = < 0x40006400 0x400 >, < 0x4000b400 0x350 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:37 */ reg-names = "m_can", "message_ram"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:38 */ interrupts = < 0x15 0x0 >, < 0x16 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:39 */ interrupt-names = "int0", "int1"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:40 */ clocks = < &rcc 0x3c 0x1000 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:41 */ bosch,mram-cfg = < 0x0 0x1c 0x8 0x3 0x3 0x0 0x3 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:42 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:43 */ }; /* node '/soc/can@40006800' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:46 */ fdcan2: can@40006800 { compatible = "st,stm32-fdcan"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:47 */ reg = < 0x40006800 0x400 >, < 0x4000b750 0x350 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:48 */ reg-names = "m_can", "message_ram"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:49 */ interrupts = < 0x15 0x0 >, < 0x16 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:50 */ interrupt-names = "int0", "int1"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:51 */ bosch,mram-cfg = < 0x0 0x1c 0x8 0x3 0x3 0x0 0x3 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:53 */ clocks = < &rcc 0x3c 0x1000 >, < &rcc 0xb 0x1280058 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:113 */ pinctrl-0 = < &fdcan2_rx_pb0 &fdcan2_tx_pb1 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:115 */ pinctrl-names = "default"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:116 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:117 */ }; /* node '/soc/serial@40005000' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:57 */ usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:58 */ reg = < 0x40005000 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:59 */ clocks = < &rcc 0x3c 0x100 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:60 */ resets = < &rctl 0x588 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:61 */ interrupts = < 0x1d 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:62 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:63 */ }; /* node '/soc/serial@40013c00' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:66 */ usart6: serial@40013c00 { compatible = "st,stm32-usart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:67 */ reg = < 0x40013c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:68 */ clocks = < &rcc 0x3c 0x200 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:69 */ resets = < &rctl 0x589 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:70 */ interrupts = < 0x1d 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:71 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:72 */ }; /* node '/soc/serial@40008400' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:75 */ lpuart2: serial@40008400 { compatible = "st,stm32-lpuart", "st,stm32-uart"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:76 */ reg = < 0x40008400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:77 */ clocks = < &rcc 0x3c 0x80 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:78 */ resets = < &rctl 0x587 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:79 */ interrupts = < 0x1c 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:80 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:81 */ }; /* node '/soc/timers@40000800' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:84 */ timers4: timers@40000800 { compatible = "st,stm32-timers"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:85 */ reg = < 0x40000800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:86 */ clocks = < &rcc 0x3c 0x4 >, < &rcc 0x9 0xff >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:87 */ resets = < &rctl 0x582 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:89 */ interrupts = < 0x10 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:90 */ interrupt-names = "global"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:91 */ st,prescaler = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:92 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:93 */ /* node '/soc/timers@40000800/pwm' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:95 */ pwm { compatible = "st,stm32-pwm"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:96 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:97 */ #pwm-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:98 */ }; /* node '/soc/timers@40000800/qdec' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:101 */ qdec { compatible = "st,stm32-qdec"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:102 */ st,input-filter-level = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:103 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:104 */ }; }; /* node '/soc/i2c@40008800' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:108 */ i2c3: i2c@40008800 { compatible = "st,stm32-i2c-v2"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:109 */ clock-frequency = < 0x186a0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:110 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:111 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:112 */ reg = < 0x40008800 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:113 */ clocks = < &rcc 0x3c 0x800000 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:114 */ interrupts = < 0x18 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:115 */ interrupt-names = "combined"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:116 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:117 */ phandle = < 0x16 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:177 */ }; /* node '/soc/spi@40003c00' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:120 */ spi3: spi@40003c00 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:121 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:122 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:123 */ reg = < 0x40003c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:124 */ clocks = < &rcc 0x3c 0x8000 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:125 */ interrupts = < 0x1a 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:126 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:127 */ }; /* node '/soc/dma@40020400' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:130 */ dma2: dma@40020400 { compatible = "st,stm32-dma-v2"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:131 */ #dma-cells = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:132 */ reg = < 0x40020400 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:133 */ interrupts = < 0xb 0x0 0xb 0x0 0xb 0x0 0xb 0x0 0xb 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:134 */ clocks = < &rcc 0x38 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:135 */ dma-requests = < 0x5 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:136 */ dma-offset = < 0x7 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:137 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:138 */ }; /* node '/soc/usb@40005c00' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:146 */ usb: zephyr_udc0: usb@40005c00 { compatible = "st,stm32-usb"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:147 */ reg = < 0x40005c00 0x400 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:148 */ interrupts = < 0x8 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:149 */ interrupt-names = "usb"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:150 */ num-bidir-endpoints = < 0x8 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:151 */ ram-size = < 0x800 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:152 */ maximum-speed = "full-speed"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:153 */ phys = < &usb_fs_phy >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:154 */ clocks = < &rcc 0x3c 0x2000 >, < &rcc 0x5 0x2c0058 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:155 */ pinctrl-0 = < &usb_dm_pa11 &usb_dp_pa12 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:90 */ pinctrl-names = "default"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:91 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:92 */ }; }; /* node '/cpus' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:31 */ cpus { #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:32 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:33 */ /* node '/cpus/cpu@0' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:35 */ cpu0: cpu@0 { device_type = "cpu"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:36 */ compatible = "arm,cortex-m0+"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:37 */ reg = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:38 */ cpu-power-states = < &stop0 &stop1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:39 */ }; /* node '/cpus/power-states' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:42 */ power-states { /* node '/cpus/power-states/state0' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:43 */ stop0: state0 { compatible = "zephyr,power-state"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:44 */ power-state-name = "suspend-to-idle"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:45 */ substate-id = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:46 */ min-residency-us = < 0x14 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:47 */ phandle = < 0x10 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:39 */ }; /* node '/cpus/power-states/state1' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:50 */ stop1: state1 { compatible = "zephyr,power-state"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:51 */ power-state-name = "suspend-to-idle"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:52 */ substate-id = < 0x2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:53 */ min-residency-us = < 0x64 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:54 */ phandle = < 0x11 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:39 */ }; }; }; /* node '/memory@20000000' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:59 */ sram0: memory@20000000 { compatible = "zephyr,memory-region", "mmio-sram"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:60 */ zephyr,memory-region = "SRAM0"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:61 */ reg = < 0x20000000 0x24000 >; /* in zephyr\dts\arm\st\g0\stm32g0b1Xe.dtsi:11 */ }; /* node '/clocks' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:64 */ clocks { /* node '/clocks/clk-hse' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:65 */ clk_hse: clk-hse { #clock-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:66 */ compatible = "st,stm32-hse-clock"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:67 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:68 */ }; /* node '/clocks/clk-hsi' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:71 */ clk_hsi: clk-hsi { #clock-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:72 */ compatible = "st,stm32g0-hsi-clock"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:73 */ hsi-div = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:74 */ clock-frequency = < 0xf42400 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:75 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:64 */ phandle = < 0x12 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:78 */ }; /* node '/clocks/clk-lse' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:79 */ clk_lse: clk-lse { #clock-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:80 */ compatible = "st,stm32-lse-clock"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:81 */ clock-frequency = < 0x8000 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:82 */ driving-capability = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:83 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:84 */ }; /* node '/clocks/clk-lsi' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:87 */ clk_lsi: clk-lsi { #clock-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:88 */ compatible = "fixed-clock"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:89 */ clock-frequency = < 0x7d00 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:90 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:60 */ }; /* node '/clocks/pll' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:94 */ pll: pll { #clock-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:95 */ compatible = "st,stm32g0-pll-clock"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:96 */ div-m = < 0x1 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:73 */ mul-n = < 0x8 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:74 */ div-p = < 0x2 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:75 */ div-q = < 0x2 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:76 */ div-r = < 0x2 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:77 */ clocks = < &clk_hsi >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:78 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:79 */ phandle = < 0x3 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:83 */ }; /* node '/clocks/clk-hsi48' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:14 */ clk_hsi48: clk-hsi48 { #clock-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:15 */ compatible = "st,stm32-hsi48-clock"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:16 */ clock-frequency = < 0x2dc6c00 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:17 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:68 */ crs-usb-sof; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:69 */ }; }; /* node '/mcos' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:101 */ mcos { /* node '/mcos/mco1' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:102 */ mco1: mco1 { compatible = "st,stm32-clock-mco"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:103 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:104 */ }; /* node '/mcos/mco2' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:107 */ mco2: mco2 { compatible = "st,stm32-clock-mco"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:108 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:109 */ }; }; /* node '/dietemp' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:531 */ die_temp: dietemp { compatible = "st,stm32-temp-cal"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:532 */ ts-cal1-addr = < 0x1fff75a8 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:533 */ ts-cal2-addr = < 0x1fff75ca >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:534 */ ts-cal1-temp = < 0x1e >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:535 */ ts-cal2-temp = < 0x82 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:536 */ ts-cal-vrefanalog = < 0xbb8 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:537 */ io-channels = < &adc1 0xc >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:538 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:121 */ }; /* node '/vref' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:542 */ vref: vref { compatible = "st,stm32-vref"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:543 */ vrefint-cal-addr = < 0x1fff75aa >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:544 */ vrefint-cal-mv = < 0xbb8 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:545 */ io-channels = < &adc1 0xd >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:546 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:125 */ }; /* node '/vbat' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:550 */ vbat: vbat { compatible = "st,stm32-vbat"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:551 */ ratio = < 0x3 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:552 */ io-channels = < &adc1 0xe >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:553 */ status = "okay"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:129 */ }; /* node '/smbus1' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:557 */ smbus1: smbus1 { compatible = "st,stm32-smbus"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:558 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:559 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:560 */ i2c = < &i2c1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:561 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:562 */ }; /* node '/smbus2' defined in zephyr\dts\arm\st\g0\stm32g0.dtsi:565 */ smbus2: smbus2 { compatible = "st,stm32-smbus"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:566 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:567 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:568 */ i2c = < &i2c2 >; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:569 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0.dtsi:570 */ }; /* node '/usbphy' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:168 */ usb_fs_phy: usbphy { compatible = "usb-nop-xceiv"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:169 */ #phy-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:170 */ phandle = < 0xd >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:154 */ }; /* node '/smbus3' defined in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:173 */ smbus3: smbus3 { compatible = "st,stm32-smbus"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:174 */ #address-cells = < 0x1 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:175 */ #size-cells = < 0x0 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:176 */ i2c = < &i2c3 >; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:177 */ status = "disabled"; /* in zephyr\dts\arm\st\g0\stm32g0b1.dtsi:178 */ }; /* node '/leds' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:26 */ leds: leds { compatible = "gpio-leds"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:27 */ /* node '/leds/led_0' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:28 */ status_led: led_0 { gpios = < &gpiob 0x4 0x0 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:29 */ label = "Status LED"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:30 */ }; }; /* node '/gpio_keys' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:34 */ gpio_keys { compatible = "gpio-keys"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:35 */ /* node '/gpio_keys/pfet1' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:36 */ pfet1: pfet1 { label = "PFET1"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:37 */ gpios = < &gpioa 0x8 0x0 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:38 */ zephyr,code = < 0x2 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:39 */ }; /* node '/gpio_keys/pfet2' defined in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:41 */ pfet2: pfet2 { label = "PFET2"; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:42 */ gpios = < &gpiob 0x2 0x0 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:43 */ zephyr,code = < 0x3 >; /* in projects\EWS\firmware\canfd_cdc_composite\boards\arm\ews\ews.dts:44 */ }; }; };