Add initial CAN FD CDC composite firmware

- Custom board definition for STM32G0B1KBU6 (ews_board)
- Zephyr-based firmware with modular architecture
- USB composite device: gs_usb CAN FD + CDC ACM interfaces
- PFET control via CDC text commands (PA8, PB2)
- Status LED on PB4, CAN FD on PB0/PB1
- No external crystal - uses HSI with USB clock recovery
- Ready for build testing with: west build -b ews_board
This commit is contained in:
2025-12-08 11:27:15 +01:00
parent 69b8cb0b79
commit 3d328fb7a2
14 changed files with 652 additions and 0 deletions

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identifier: ews_board
name: EWS Board
type: mcu
arch: arm
family: stm32
series: stm32g0x
socs:
- name: stm32g0b1xx
testing:
default: true

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# EWS Board
## Overview
The EWS Board is based on the STM32G0B1KBU6 microcontroller in UFQFPN32 package.
## Hardware Features
- STM32G0B1KBU6 MCU (Arm Cortex-M0+ core, 128 KB Flash, 36 KB RAM)
- Internal HSI oscillator with USB clock recovery
- USB 2.0 Full Speed interface
- CAN FD interface
- Status LED on PB4
- Two PFET control outputs (PA8, PB2)
## Pin Configuration
| Function | Pin | Notes |
|----------|-----|-------|
| Status LED | PB4 | Active high |
| PFET1 Control | PA8 | Active high |
| PFET2 Control | PB2 | Active high |
| CAN RX | PB0 | FDCAN1_RX |
| CAN TX | PB1 | FDCAN1_TX |
| USB D- | PA11 | USB_DM |
| USB D+ | PA12 | USB_DP |
## Clock Configuration
The board uses the internal HSI oscillator (16 MHz) with PLL to generate:
- System clock: 64 MHz
- USB clock: 48 MHz (from PLL Q output)
- CAN clock: 64 MHz
No external crystal is used; USB clock recovery ensures accurate timing for USB communication.
## Programming and Debugging
The board supports programming via:
- USB DFU (built-in STM32 bootloader)
- SWD interface (if exposed)
## Building Firmware
```bash
west build -b ews_board
```

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/dts-v1/;
#include <st/g0/stm32g0b1Xb.dtsi>
#include <st/g0/stm32g0b1k(b-c-e)ux-pinctrl.dtsi>
/ {
model = "EWS Board STM32G0B1KBU6";
compatible = "ews,ews-board";
chosen {
zephyr,console = &cdc_acm_uart0;
zephyr,shell-uart = &cdc_acm_uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &fdcan1;
};
leds {
compatible = "gpio-leds";
status_led: led_0 {
gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>;
label = "Status LED";
};
};
pfets {
compatible = "gpio-leds";
pfet1: pfet_1 {
gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>;
label = "PFET1 Control";
};
pfet2: pfet_2 {
gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
label = "PFET2 Control";
};
};
aliases {
led0 = &status_led;
pfet0 = &pfet1;
pfet1 = &pfet2;
};
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <8>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&fdcan1 {
pinctrl-0 = <&fdcan1_rx_pb0 &fdcan1_tx_pb1>;
pinctrl-names = "default";
bus-speed = <500000>;
bus-speed-data = <2000000>;
status = "okay";
};
&usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00002000>;
};
slot0_partition: partition@2000 {
label = "image-0";
reg = <0x00002000 0x0001E000>;
};
};
};

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# EWS Board Configuration
CONFIG_SOC_SERIES_STM32G0X=y
CONFIG_SOC_STM32G0B1XX=y
# Clock configuration - USB clock sync, no external crystal
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_STM32_HSI=y
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=8
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
# USB 48MHz from PLL
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
# Enable GPIO
CONFIG_GPIO=y
# Enable CAN
CONFIG_CAN=y