# 0 "C:/Users/iteedi/zephyrproject/zephyr/misc/empty_file.c"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "C:/Users/iteedi/zephyrproject/projects/EWS/firmware/canfd_cdc_composite/boards/arm/ews/ews.dts" 1

/dts-v1/;
# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0b1Xe.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0b1.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g071.dtsi" 1 3 4
# 9 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g071.dtsi" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g051.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g031.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g030.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 1 3 4
# 11 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/armv6-m.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/common/skeleton.dtsi" 1 3 4
# 9 "C:/Users/iteedi/zephyrproject/zephyr/dts/common/skeleton.dtsi" 3 4
/ {
 #address-cells = <1>;
 #size-cells = <1>;

 chosen {};

 aliases {};
};
# 4 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/armv6-m.dtsi" 2 3 4

/ {
 soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  interrupt-parent = <&nvic>;
  ranges;

  nvic: interrupt-controller@e000e100 {
   #address-cells = <1>;
   compatible = "arm,v6m-nvic";
   reg = <0xe000e100 0xc00>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  systick: timer@e000e010 {
   compatible = "arm,armv6m-systick";
   reg = <0xe000e010 0x10>;
  };
 };
};
# 12 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h" 1 3 4
# 9 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32_common_clocks.h" 1 3 4
# 10 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h" 2 3 4
# 13 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/gpio/gpio.h" 1 3 4
# 14 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/i2c/i2c.h" 1 3 4
# 15 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/pwm/pwm.h" 1 3 4
# 16 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/dma/stm32_dma.h" 1 3 4
# 17 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 1 3 4
# 9 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 1 3 4
# 19 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 1 3 4
# 34 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 1 3 4
# 18 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 1 3 4
# 1083 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_listify.h" 1 3 4
# 1084 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 2 3 4
# 19 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 162 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal_is_eq.h" 1 3 4
# 163 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 193 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_inc.h" 1 3 4
# 194 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_dec.h" 1 3 4
# 197 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_x2.h" 1 3 4
# 200 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 35 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 2 3 4
# 20 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 2 3 4
# 10 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 2 3 4
# 18 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/stm32l4_adc.h" 1 3 4
# 9 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/stm32l4_adc.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/stm32_adc.h" 1 3 4
# 10 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/stm32l4_adc.h" 2 3 4
# 19 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/power/stm32_pwr.h" 1 3 4
# 20 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/pwm/stm32_pwm.h" 1 3 4
# 21 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/sensor/qdec_stm32.h" 1 3 4
# 22 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32g0_reset.h" 1 3 4
# 10 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32g0_reset.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32-common.h" 1 3 4
# 11 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32g0_reset.h" 2 3 4
# 23 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/common/freq.h" 1 3 4
# 24 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/dts/common/mem.h" 1 3 4
# 25 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0.dtsi" 2 3 4

/ {
 chosen {
  zephyr,flash-controller = &flash;
 };

 cpus {
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-m0+";
   reg = <0>;
   cpu-power-states = <&stop0 &stop1>;
  };

  power-states {
   stop0: state0 {
    compatible = "zephyr,power-state";
    power-state-name = "suspend-to-idle";
    substate-id = <1>;
    min-residency-us = <20>;
   };

   stop1: state1 {
    substate-id = <2>;
    min-residency-us = <100>;
   };
  };
 };

 sram0: memory@20000000 {
  compatible = "zephyr,memory-region", "mmio-sram";
  zephyr,memory-region = "SRAM0";
 };

 clocks {
  clk_hse: clk-hse {
   #clock-cells = <0>;
   compatible = "st,stm32-hse-clock";
   status = "disabled";
  };

  clk_hsi: clk-hsi {
   compatible = "st,stm32g0-hsi-clock";
   hsi-div = <1>;
   clock-frequency = <(((16) * 1000) * 1000)>;
  };

  clk_lse: clk-lse {
   compatible = "st,stm32-lse-clock";
   clock-frequency = <32768>;
   driving-capability = <0>;
  };

  clk_lsi: clk-lsi {
   compatible = "fixed-clock";
   clock-frequency = <((32) * 1000)>;
  };

  pll: pll {
   compatible = "st,stm32g0-pll-clock";
  };
 };

 mcos {
  mco1: mco1 {
   compatible = "st,stm32-clock-mco";
  };

  mco2: mco2 {
  };
 };

 soc {
  flash: flash-controller@40022000 {
   compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
   reg = <0x40022000 0x400>;
   interrupts = <3 0>;
   clocks = <&rcc (0x038) (1 << 8)>;

   #size-cells = <1>;

   flash0: flash@8000000 {
    compatible = "st,stm32-nv-flash", "soc-nv-flash";

    write-block-size = <8>;
    erase-block-size = <2048>;

    max-erase-time = <40>;
   };
  };

  rcc: rcc@40021000 {
   compatible = "st,stm32f0-rcc";
   #clock-cells = <2>;
   reg = <0x40021000 0x400>;

   rctl: reset-controller {
    compatible = "st,stm32-rcc-rctl";
    #reset-cells = <1>;
   };
  };

  exti: interrupt-controller@40021800 {
   compatible = "st,stm32g0-exti", "st,stm32-exti";
   #interrupt-cells = <1>;
   #address-cells = <0>;
   reg = <0x40021800 0x400>;
   clocks = <&rcc (0x040) (1 << 0)>;
   num-lines = <32>;
   interrupts = <5 0>, <6 0>, <7 0>;
   interrupt-names = "line0-1", "line2-3", "line4-15";
   line-ranges = <0 2>, <2 2>, <4 12>;
  };

  pinctrl: pin-controller@50000000 {
   compatible = "st,stm32-pinctrl";
   reg = <0x50000000 0x2000>;

   gpioa: gpio@50000000 {
    compatible = "st,stm32-gpio";
    gpio-controller;
    #gpio-cells = <2>;
    reg = <0x50000000 0x400>;
    clocks = <&rcc (0x034) (1 << 0)>;
   };

   gpiob: gpio@50000400 {
    reg = <0x50000400 0x400>;
    clocks = <&rcc (0x034) (1 << 1)>;
   };

   gpioc: gpio@50000800 {
    reg = <0x50000800 0x400>;
    clocks = <&rcc (0x034) (1 << 2)>;
   };

   gpiod: gpio@50000c00 {
    reg = <0x50000c00 0x400>;
    clocks = <&rcc (0x034) (1 << 3)>;
   };

   gpiof: gpio@50001400 {
    reg = <0x50001400 0x400>;
    clocks = <&rcc (0x034) (1 << 5)>;
   };
  };

  rtc: rtc@40002800 {
   compatible = "st,stm32-rtc";
   reg = <0x40002800 0x400>;
   interrupts = <2 0>;
   clocks = <&rcc (0x03c) (1 << 10)>;
   prescaler = <32768>;
   alarms-count = <2>;
   alrm-exti-line = <19>;

   bbram: backup_regs {
    compatible = "st,stm32-bbram";
    st,backup-regs = <5>;
    status = "disabled";
   };
  };

  iwdg: watchdog@40003000 {
   compatible = "st,stm32-watchdog";
   reg = <0x40003000 0x400>;
  };

  wwdg: watchdog@40002c00 {
   compatible = "st,stm32-window-watchdog";
   reg = <0x40002C00 0x400>;
   clocks = <&rcc (0x03c) (1 << 11)>;
   interrupts = <0 2>;
  };

  usart1: serial@40013800 {
   compatible = "st,stm32-usart", "st,stm32-uart";
   reg = <0x40013800 0x400>;
   clocks = <&rcc (0x040) (1 << 14)>;
   resets = <&rctl (((0x30) << 5U) | (14))>;
   interrupts = <27 0>;
  };

  usart2: serial@40004400 {
   reg = <0x40004400 0x400>;
   clocks = <&rcc (0x03c) (1 << 17)>;
   resets = <&rctl (((0x2C) << 5U) | (17))>;
   interrupts = <28 0>;
  };

  lptim1: timers@40007c00 {
   compatible = "st,stm32-lptim";
   clocks = <&rcc (0x03c) (1 << 31)>;
   #size-cells = <0>;
   reg = <0x40007c00 0x400>;
   interrupts = <17 1>;
   interrupt-names = "wakeup";
  };

  timers1: timers@40012c00 {
   compatible = "st,stm32-timers";
   reg = <0x40012C00 0x400>;
   clocks = <&rcc (0x040) (1 << 11)>,
     <&rcc ((((((0x003 + 1) + 1) + 1) + 1) + 1) + 1) 0xFF>;
   resets = <&rctl (((0x30) << 5U) | (11))>;
   interrupts = <13 0>, <14 0>;
   interrupt-names = "brk_up_trg_com", "cc";
   st,prescaler = <0>;

   pwm {
    compatible = "st,stm32-pwm";
    #pwm-cells = <3>;
   };

   counter {
    compatible = "st,stm32-counter";
   };

   qdec {
    compatible = "st,stm32-qdec";
    st,input-filter-level = <0>;
   };
  };

  timers3: timers@40000400 {
   reg = <0x40000400 0x400>;
   clocks = <&rcc (0x03c) (1 << 1)>,
   resets = <&rctl (((0x2C) << 5U) | (1))>;
   interrupts = <16 0>;
   interrupt-names = "global";

   pwm {
   };

   counter {
   };

   qdec {
   };
  };

  timers14: timers@40002000 {
   reg = <0x40002000 0x400>;
   clocks = <&rcc (0x040) (1 << 15)>,
   resets = <&rctl (((0x30) << 5U) | (15))>;
   interrupts = <19 0>;

   pwm {
   };

   counter {
   };
  };

  timers16: timers@40014400 {
   reg = <0x40014400 0x400>;
   clocks = <&rcc (0x040) (1 << 17)>,
   resets = <&rctl (((0x30) << 5U) | (17))>;
   interrupts = <21 0>;

   pwm {
   };

   counter {
   };
  };

  timers17: timers@40014800 {
   reg = <0x40014800 0x400>;
   clocks = <&rcc (0x040) (1 << 18)>,
   resets = <&rctl (((0x30) << 5U) | (18))>;
   interrupts = <22 0>;

   pwm {
   };

   counter {
   };
  };

  i2c1: i2c@40005400 {
   compatible = "st,stm32-i2c-v2";
   clock-frequency = <100000>;
   reg = <0x40005400 0x400>;
   clocks = <&rcc (0x03c) (1 << 21)>;
   interrupts = <23 0>;
   interrupt-names = "combined";
  };

  i2c2: i2c@40005800 {
   reg = <0x40005800 0x400>;
   clocks = <&rcc (0x03c) (1 << 22)>;
   interrupts = <24 0>;
  };

  spi1: spi@40013000 {
   compatible = "st,stm32-spi-fifo", "st,stm32-spi";
   reg = <0x40013000 0x400>;
   clocks = <&rcc (0x040) (1 << 12)>;
   interrupts = <25 0>;
  };

  spi2: spi@40003800 {
   reg = <0x40003800 0x400>;
   clocks = <&rcc (0x03c) (1 << 14)>;
   interrupts = <26 0>;
  };

  adc1: adc@40012400 {
   compatible = "st,stm32-adc";
   reg = <0x40012400 0x400>;
   clocks = <&rcc (0x040) (1 << 20)>;
   clock-names = "adcx";
   interrupts = <12 0>;
   #io-channel-cells = <1>;
   resolutions = <((((0x0C) & ((1UL << (8)) - 1UL)) << 0U) | (((3) & ((1UL << (5)) - 1UL)) << 8U) | (((((1UL << (2)) - 1UL)) & ((1UL << (3)) - 1UL)) << 13U) | (((0x00) & ((1UL << (3)) - 1UL)) << 16U) | (((12) & ((1UL << (13)) - 1UL)) << 19U))
           ((((0x0C) & ((1UL << (8)) - 1UL)) << 0U) | (((3) & ((1UL << (5)) - 1UL)) << 8U) | (((((1UL << (2)) - 1UL)) & ((1UL << (3)) - 1UL)) << 13U) | (((0x01) & ((1UL << (3)) - 1UL)) << 16U) | (((10) & ((1UL << (13)) - 1UL)) << 19U))
           ((((0x0C) & ((1UL << (8)) - 1UL)) << 0U) | (((3) & ((1UL << (5)) - 1UL)) << 8U) | (((((1UL << (2)) - 1UL)) & ((1UL << (3)) - 1UL)) << 13U) | (((0x02) & ((1UL << (3)) - 1UL)) << 16U) | (((8) & ((1UL << (13)) - 1UL)) << 19U))
           ((((0x0C) & ((1UL << (8)) - 1UL)) << 0U) | (((3) & ((1UL << (5)) - 1UL)) << 8U) | (((((1UL << (2)) - 1UL)) & ((1UL << (3)) - 1UL)) << 13U) | (((0x03) & ((1UL << (3)) - 1UL)) << 16U) | (((6) & ((1UL << (13)) - 1UL)) << 19U))>;

   sampling-times = <3 5 8 13 20 40 80 161>;
   num-sampling-time-common-channels = <2>;
   st,adc-sequencer = "fixed";
   st,adc-oversampler = "minimal";
   st,adc-internal-regulator = "startup-sw-delay";
  };

  dma1: dma@40020000 {
   compatible = "st,stm32-dma-v2";
   #dma-cells = <3>;
   reg = <0x40020000 0x400>;
   interrupts = <9 0 10 0 10 0 11 0 11 0>;
   clocks = <&rcc (0x038) (1 << 0)>;
   dma-requests = <5>;
   dma-offset = <0>;
  };

  dmamux1: dmamux@40020800 {
   compatible = "st,stm32-dmamux";
   reg = <0x40020800 0x800>;
   interrupts = <11 0>;
   dma-channels = <5>;
   dma-generators = <4>;
   dma-requests = <49>;
  };

  pwr: power@40007000 {
   compatible = "st,stm32-pwr";
   reg = <0x40007000 0x400>;

   wkup-pins-nb = <6>;
   wkup-pins-pol;
   wkup-pins-pupd;

   wkup-pin@1 {
    reg = <0x1>;
    wkup-gpios = <&gpioa 0 (1UL << (0))>;
   };

   wkup-pin@2 {
    reg = <0x2>;
    wkup-gpios = <&gpioa 4 (1UL << (0))>,
          <&gpioc 13 (1UL << (0))>;
   };

   wkup-pin@4 {
    reg = <0x4>;
    wkup-gpios = <&gpioa 2 (1UL << (0))>;
   };

   wkup-pin@5 {
    reg = <0x5>;
    wkup-gpios = <&gpioc 5 (1UL << (0))>;
   };

   wkup-pin@6 {
    reg = <0x6>;
    wkup-gpios = <&gpiob 5 (1UL << (0))>;
   };
  };
 };

 die_temp: dietemp {
  compatible = "st,stm32-temp-cal";
  ts-cal1-addr = <0x1FFF75A8>;
  ts-cal2-addr = <0x1FFF75CA>;
  ts-cal1-temp = <30>;
  ts-cal2-temp = <130>;
  ts-cal-vrefanalog = <3000>;
  io-channels = <&adc1 12>;
  status = "disabled";
 };

 vref: vref {
  compatible = "st,stm32-vref";
  vrefint-cal-addr = <0x1FFF75AA>;
  vrefint-cal-mv = <3000>;
  io-channels = <&adc1 13>;
 };

 vbat: vbat {
  compatible = "st,stm32-vbat";
  ratio = <3>;
  io-channels = <&adc1 14>;
 };

 smbus1: smbus1 {
  compatible = "st,stm32-smbus";
  i2c = <&i2c1>;
 };

 smbus2: smbus2 {
  i2c = <&i2c2>;
 };
};

&nvic {
 arm,num-irq-priority-bits = <2>;
};
# 8 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g030.dtsi" 2 3 4

/ {
 soc {
  compatible = "st,stm32g030", "st,stm32g0", "simple-bus";
 };
};
# 9 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g031.dtsi" 2 3 4

/ {
 soc {
  compatible = "st,stm32g031", "st,stm32g0", "simple-bus";

  lpuart1: serial@40008000 {
   compatible = "st,stm32-lpuart", "st,stm32-uart";
   reg = <0x40008000 0x400>;
   clocks = <&rcc (0x03c) (1 << 20)>;
   resets = <&rctl (((0x2C) << 5U) | (20))>;
   interrupts = <29 0>;
  };

     <&rcc ((((((0x003 + 1) + 1) + 1) + 1) + 1) + 1) ((((0x54) & 0xFFFFU) << 0U) | (((22) & 0x1FU) << 16U) | ((((22) - (22)) & 0x3U) << 21U) | ((((0)) & 0xFFU) << 24U))>;
  };

  timers2: timers@40000000 {
   reg = <0x40000000 0x400>;
   clocks = <&rcc (0x03c) (1 << 0)>,
   resets = <&rctl (((0x2C) << 5U) | (0))>;
   interrupts = <15 0>;

   pwm {
   };

   qdec {
   };
  };
 };
};
# 8 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g051.dtsi" 2 3 4

/ {
 soc {
  compatible = "st,stm32g051", "st,stm32g0", "simple-bus";

  timers6: timers@40001000 {
   reg = <0x40001000 0x400>;
   clocks = <&rcc (0x03c) (1 << 4)>,
   resets = <&rctl (((0x2C) << 5U) | (4))>;
   interrupts = <17 0>;

   counter {
   };
  };

  timers7: timers@40001400 {
   reg = <0x40001400 0x400>;
   clocks = <&rcc (0x03c) (1 << 5)>,
   resets = <&rctl (((0x2C) << 5U) | (5))>;
   interrupts = <18 0>;

   counter {
   };
  };

  timers15: timers@40014000 {
   reg = <0x40014000 0x400>;
   clocks = <&rcc (0x040) (1 << 16)>,
     <&rcc ((((((0x003 + 1) + 1) + 1) + 1) + 1) + 1) ((((0x54) & 0xFFFFU) << 0U) | (((24) & 0x1FU) << 16U) | ((((24) - (24)) & 0x3U) << 21U) | ((((0)) & 0xFFU) << 24U))>;
   resets = <&rctl (((0x30) << 5U) | (16))>;
   interrupts = <20 0>;

   pwm {
   };

   counter {
   };
  };

  dac1: dac@40007400 {
   compatible = "st,stm32-dac";
   reg = <0x40007400 0x400>;
   clocks = <&rcc (0x03c) (1 << 29)>;
  };

   interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
   dma-requests = <7>;
  };

   dma-channels = <7>;
  };
 };
};
# 10 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g071.dtsi" 2 3 4

/ {
 soc {
  compatible = "st,stm32g071", "st,stm32g0", "simple-bus";

  usart3: serial@40004800 {
   reg = <0x40004800 0x400>;
   clocks = <&rcc (0x03c) (1 << 18)>;
   resets = <&rctl (((0x2C) << 5U) | (18))>;
  };

  usart4: serial@40004c00 {
   reg = <0x40004c00 0x400>;
   clocks = <&rcc (0x03c) (1 << 19)>;
   resets = <&rctl (((0x2C) << 5U) | (19))>;
  };

   dma-requests = <57>;
  };

  ucpd1: ucpd@4000a000 {
   compatible = "st,stm32-ucpd";
   reg = <0x4000a000 0x400>;
   clocks = <&rcc (0x03c) (1 << 25)>;
   interrupts = <8 0>;
  };

  ucpd2: ucpd@4000a400 {
   reg = <0x4000a400 0x400>;
   clocks = <&rcc (0x03c) (1 << 26)>;
  };
 };
};
# 9 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0b1.dtsi" 2 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g0_b1x_c1x_clock.h" 1 3 4
# 10 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0b1.dtsi" 2 3 4

/ {
 clocks {
  clk_hsi48: clk-hsi48 {
   compatible = "st,stm32-hsi48-clock";
   clock-frequency = <(((48) * 1000) * 1000)>;
  };
 };

 soc {
  compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";

   gpioe: gpio@50001000 {
    reg = <0x50001000 0x400>;
    clocks = <&rcc (0x034) (1 << 4)>;
   };
  };

  fdcan1: can@40006400 {
   compatible = "st,stm32-fdcan";
   reg = <0x40006400 0x400>, <0x4000b400 0x350>;
   reg-names = "m_can", "message_ram";
   interrupts = <21 0>, <22 0>;
   interrupt-names = "int0", "int1";
   clocks = <&rcc (0x03c) (1 << 12)>;
   bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
  };

  fdcan2: can@40006800 {
   reg = <0x40006800 0x400>, <0x4000b750 0x350>;
  };

  usart5: serial@40005000 {
   reg = <0x40005000 0x400>;
   clocks = <&rcc (0x03c) (1 << 8)>;
   resets = <&rctl (((0x2C) << 5U) | (8))>;
  };

  usart6: serial@40013c00 {
   reg = <0x40013c00 0x400>;
   clocks = <&rcc (0x03c) (1 << 9)>;
   resets = <&rctl (((0x2C) << 5U) | (9))>;
  };

  lpuart2: serial@40008400 {
   reg = <0x40008400 0x400>;
   clocks = <&rcc (0x03c) (1 << 7)>;
   resets = <&rctl (((0x2C) << 5U) | (7))>;
  };

  timers4: timers@40000800 {
   reg = <0x40000800 0x400>;
   clocks = <&rcc (0x03c) (1 << 2)>,
   resets = <&rctl (((0x2C) << 5U) | (2))>;

   pwm {
   };

   qdec {
   };
  };

  i2c3: i2c@40008800 {
   reg = <0x40008800 0x400>;
   clocks = <&rcc (0x03c) (1 << 23)>;
  };

  spi3: spi@40003c00 {
   reg = <0x40003c00 0x400>;
   clocks = <&rcc (0x03c) (1 << 15)>;
   interrupts = <26 3>;
  };

  dma2: dma@40020400 {
   reg = <0x40020400 0x400>;
   interrupts = <11 0 11 0 11 0 11 0 11 0>;
   clocks = <&rcc (0x038) (1 << 1)>;
   dma-offset = <7>;
  };

   dma-channels = <12>;
   dma-requests = <73>;
  };

  usb: usb@40005c00 {
   compatible = "st,stm32-usb";
   reg = <0x40005c00 0x400>;
   interrupt-names = "usb";
   num-bidir-endpoints = <8>;
   ram-size = <2048>;
   maximum-speed = "full-speed";
   phys = <&usb_fs_phy>;
   clocks = <&rcc (0x03c) (1 << 13)>,
     <&rcc ((0x003 + 1) + 1) ((((0x58) & 0xFFFFU) << 0U) | (((12) & 0x1FU) << 16U) | ((((13) - (12)) & 0x3U) << 21U) | ((((0)) & 0xFFU) << 24U))>;
  };

   wkup-pin@3 {
    reg = <0x3>;
    wkup-gpios = <&gpioe 6 (1UL << (0))>;
   };
  };
 };

 usb_fs_phy: usbphy {
  compatible = "usb-nop-xceiv";
  #phy-cells = <0>;
 };

 smbus3: smbus3 {
  i2c = <&i2c3>;
 };
};

&exti {
 num-lines = <64>;
};
# 8 "C:/Users/iteedi/zephyrproject/zephyr/dts/arm/st/g0/stm32g0b1Xe.dtsi" 2 3 4

/ {
  reg = <0x20000000 ((144) * 1024)>;
 };

 soc {
  flash-controller@40022000 {
    reg = <0x08000000 ((512) * 1024)>;
   };
  };
 };
};
# 9 "C:/Users/iteedi/zephyrproject/projects/EWS/firmware/canfd_cdc_composite/boards/arm/ews/ews.dts" 2
# 1 "C:/Users/iteedi/zephyrproject/modules/hal/stm32/dts/st/g0/stm32g0b1r(b-c-e)tx-pinctrl.dtsi" 1 3 4

# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h" 1 3 4
# 10 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h" 3 4
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h" 1 3 4
# 11 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h" 2 3 4
# 8 "C:/Users/iteedi/zephyrproject/modules/hal/stm32/dts/st/g0/stm32g0b1r(b-c-e)tx-pinctrl.dtsi" 2 3 4

/ {
 soc {

   /omit-if-no-ref/ adc1_in0_pa0: adc1_in0_pa0 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in1_pa1: adc1_in1_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in2_pa2: adc1_in2_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in3_pa3: adc1_in3_pa3 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in4_pa4: adc1_in4_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in5_pa5: adc1_in5_pa5 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in6_pa6: adc1_in6_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in7_pa7: adc1_in7_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in8_pb0: adc1_in8_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in9_pb1: adc1_in9_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in10_pb2: adc1_in10_pb2 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in11_pb10: adc1_in11_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in15_pb11: adc1_in15_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in16_pb12: adc1_in16_pb12 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in17_pc4: adc1_in17_pc4 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ adc1_in18_pc5: adc1_in18_pc5 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa0: analog_pa0 {
   };

   /omit-if-no-ref/ analog_pa1: analog_pa1 {
   };

   /omit-if-no-ref/ analog_pa2: analog_pa2 {
   };

   /omit-if-no-ref/ analog_pa3: analog_pa3 {
   };

   /omit-if-no-ref/ analog_pa4: analog_pa4 {
   };

   /omit-if-no-ref/ analog_pa5: analog_pa5 {
   };

   /omit-if-no-ref/ analog_pa6: analog_pa6 {
   };

   /omit-if-no-ref/ analog_pa7: analog_pa7 {
   };

   /omit-if-no-ref/ analog_pa8: analog_pa8 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa9: analog_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa10: analog_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa11: analog_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa12: analog_pa12 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa13: analog_pa13 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa14: analog_pa14 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pa15: analog_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb0: analog_pb0 {
   };

   /omit-if-no-ref/ analog_pb1: analog_pb1 {
   };

   /omit-if-no-ref/ analog_pb2: analog_pb2 {
   };

   /omit-if-no-ref/ analog_pb3: analog_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb4: analog_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb5: analog_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb6: analog_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb7: analog_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb8: analog_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb9: analog_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb10: analog_pb10 {
   };

   /omit-if-no-ref/ analog_pb11: analog_pb11 {
   };

   /omit-if-no-ref/ analog_pb12: analog_pb12 {
   };

   /omit-if-no-ref/ analog_pb13: analog_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb14: analog_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pb15: analog_pb15 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc0: analog_pc0 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc1: analog_pc1 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc2: analog_pc2 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc3: analog_pc3 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc4: analog_pc4 {
   };

   /omit-if-no-ref/ analog_pc5: analog_pc5 {
   };

   /omit-if-no-ref/ analog_pc6: analog_pc6 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc7: analog_pc7 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc8: analog_pc8 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc9: analog_pc9 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc10: analog_pc10 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc11: analog_pc11 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc12: analog_pc12 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc13: analog_pc13 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc14: analog_pc14 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pc15: analog_pc15 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd0: analog_pd0 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd1: analog_pd1 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd2: analog_pd2 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd3: analog_pd3 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd4: analog_pd4 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd5: analog_pd5 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd6: analog_pd6 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd8: analog_pd8 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pd9: analog_pd9 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pf0: analog_pf0 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pf1: analog_pf1 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ analog_pf2: analog_pf2 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp1_inm_pa0: comp1_inm_pa0 {
   };

   /omit-if-no-ref/ comp1_inp_pa1: comp1_inp_pa1 {
   };

   /omit-if-no-ref/ comp1_inm_pb1: comp1_inm_pb1 {
   };

   /omit-if-no-ref/ comp1_inp_pb2: comp1_inp_pb2 {
   };

   /omit-if-no-ref/ comp1_inm_pc4: comp1_inm_pc4 {
   };

   /omit-if-no-ref/ comp1_inp_pc5: comp1_inp_pc5 {
   };

   /omit-if-no-ref/ comp2_inm_pa2: comp2_inm_pa2 {
   };

   /omit-if-no-ref/ comp2_inp_pa3: comp2_inp_pa3 {
   };

   /omit-if-no-ref/ comp2_inm_pb3: comp2_inm_pb3 {
   };

   /omit-if-no-ref/ comp2_inp_pb4: comp2_inp_pb4 {
   };

   /omit-if-no-ref/ comp2_inp_pb6: comp2_inp_pb6 {
   };

   /omit-if-no-ref/ comp2_inm_pb7: comp2_inm_pb7 {
   };

   /omit-if-no-ref/ comp3_inp_pb0: comp3_inp_pb0 {
   };

   /omit-if-no-ref/ comp3_inm_pb2: comp3_inm_pb2 {
   };

   /omit-if-no-ref/ comp3_inm_pc0: comp3_inm_pc0 {
   };

   /omit-if-no-ref/ comp3_inp_pc1: comp3_inp_pc1 {
   };

   /omit-if-no-ref/ comp1_out_pa0: comp1_out_pa0 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp1_out_pa6: comp1_out_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp1_out_pa11: comp1_out_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp1_out_pb0: comp1_out_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp1_out_pb10: comp1_out_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp2_out_pa2: comp2_out_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp2_out_pa7: comp2_out_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp2_out_pa12: comp2_out_pa12 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp2_out_pb5: comp2_out_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp2_out_pb11: comp2_out_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp3_out_pb1: comp3_out_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp3_out_pc0: comp3_out_pc0 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ comp3_out_pc2: comp3_out_pc2 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ dac1_out1_pa4: dac1_out1_pa4 {
   };

   /omit-if-no-ref/ dac1_out2_pa5: dac1_out2_pa5 {
   };

   /omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_rx_pb8: fdcan1_rx_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_rx_pc4: fdcan1_rx_pc4 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_rx_pb0: fdcan2_rx_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_rx_pc2: fdcan2_rx_pc2 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_tx_pb9: fdcan1_tx_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_tx_pc5: fdcan1_tx_pc5 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_tx_pb6: fdcan2_tx_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_tx_pb13: fdcan2_tx_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ fdcan2_tx_pc3: fdcan2_tx_pc3 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_scl_pa9: i2c1_scl_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
    bias-pull-up;
    drive-open-drain;
   };

   /omit-if-no-ref/ i2c1_scl_pb6: i2c1_scl_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_scl_pb8: i2c1_scl_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_scl_pa7: i2c2_scl_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_scl_pa9: i2c2_scl_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_scl_pa11: i2c2_scl_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_scl_pb3: i2c2_scl_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_scl_pb13: i2c2_scl_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c3_scl_pa7: i2c3_scl_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c3_scl_pb3: i2c3_scl_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c3_scl_pc0: i2c3_scl_pc0 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_sda_pa10: i2c1_sda_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_sda_pb7: i2c1_sda_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_sda_pb9: i2c1_sda_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_sda_pa6: i2c2_sda_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_sda_pa10: i2c2_sda_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_sda_pa12: i2c2_sda_pa12 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_sda_pb4: i2c2_sda_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_sda_pb14: i2c2_sda_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c3_sda_pa6: i2c3_sda_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c3_sda_pb4: i2c3_sda_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c3_sda_pc1: i2c3_sda_pc1 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_smba_pa1: i2c1_smba_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_smba_pa8: i2c2_smba_pa8 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_smba_pa15: i2c2_smba_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ck_pa1: i2s1_ck_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
    slew-rate = "very-high-speed";
   };

   /omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ck_pb3: i2s1_ck_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ck_pd8: i2s1_ck_pd8 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ck_pa0: i2s2_ck_pa0 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ck_pb8: i2s2_ck_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ck_pb13: i2s2_ck_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ck_pd1: i2s2_ck_pd1 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_mck_pa6: i2s1_mck_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_mck_pa11: i2s1_mck_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_mck_pb4: i2s1_mck_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_mck_pd5: i2s1_mck_pd5 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pa3: i2s2_mck_pa3 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pa9: i2s2_mck_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pb2: i2s2_mck_pb2 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pb6: i2s2_mck_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pb14: i2s2_mck_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pc2: i2s2_mck_pc2 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_mck_pd3: i2s2_mck_pd3 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_sd_pa2: i2s1_sd_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_sd_pa7: i2s1_sd_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_sd_pa12: i2s1_sd_pa12 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_sd_pb5: i2s1_sd_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_sd_pd6: i2s1_sd_pd6 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pa4: i2s2_sd_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pa10: i2s2_sd_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pb7: i2s2_sd_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pb11: i2s2_sd_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pb15: i2s2_sd_pb15 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pc3: i2s2_sd_pc3 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_sd_pd4: i2s2_sd_pd4 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ws_pa4: i2s1_ws_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ws_pb0: i2s1_ws_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s1_ws_pd9: i2s1_ws_pd9 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ws_pa8: i2s2_ws_pa8 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ws_pb9: i2s2_ws_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ i2s2_ws_pd0: i2s2_ws_pd0 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ sys_swdio_pa13: sys_swdio_pa13 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ sys_swclk_pa14: sys_swclk_pa14 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ rcc_mco_pa8: rcc_mco_pa8 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ rcc_mco_pa9: rcc_mco_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ rcc_mco_2_pa10: rcc_mco_2_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ rcc_mco_2_pa15: rcc_mco_2_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ rcc_mco_2_pb2: rcc_mco_2_pb2 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ rcc_mco_pf2: rcc_mco_pf2 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
    bias-pull-down;
   };

   /omit-if-no-ref/ spi1_miso_pa11: spi1_miso_pa11 {
   };

   /omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
   };

   /omit-if-no-ref/ spi1_miso_pd5: spi1_miso_pd5 {
   };

   /omit-if-no-ref/ spi2_miso_pa3: spi2_miso_pa3 {
   };

   /omit-if-no-ref/ spi2_miso_pa9: spi2_miso_pa9 {
   };

   /omit-if-no-ref/ spi2_miso_pb2: spi2_miso_pb2 {
   };

   /omit-if-no-ref/ spi2_miso_pb6: spi2_miso_pb6 {
   };

   /omit-if-no-ref/ spi2_miso_pb14: spi2_miso_pb14 {
   };

   /omit-if-no-ref/ spi2_miso_pc2: spi2_miso_pc2 {
   };

   /omit-if-no-ref/ spi2_miso_pd3: spi2_miso_pd3 {
   };

   /omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi1_mosi_pa2: spi1_mosi_pa2 {
   };

   /omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
   };

   /omit-if-no-ref/ spi1_mosi_pa12: spi1_mosi_pa12 {
   };

   /omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
   };

   /omit-if-no-ref/ spi1_mosi_pd6: spi1_mosi_pd6 {
   };

   /omit-if-no-ref/ spi2_mosi_pa4: spi2_mosi_pa4 {
   };

   /omit-if-no-ref/ spi2_mosi_pa10: spi2_mosi_pa10 {
   };

   /omit-if-no-ref/ spi2_mosi_pb7: spi2_mosi_pb7 {
   };

   /omit-if-no-ref/ spi2_mosi_pb11: spi2_mosi_pb11 {
   };

   /omit-if-no-ref/ spi2_mosi_pb15: spi2_mosi_pb15 {
   };

   /omit-if-no-ref/ spi2_mosi_pc3: spi2_mosi_pc3 {
   };

   /omit-if-no-ref/ spi2_mosi_pd4: spi2_mosi_pd4 {
   };

   /omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi1_nss_pa4: spi1_nss_pa4 {
   };

   /omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
   };

   /omit-if-no-ref/ spi1_nss_pb0: spi1_nss_pb0 {
   };

   /omit-if-no-ref/ spi1_nss_pd9: spi1_nss_pd9 {
   };

   /omit-if-no-ref/ spi2_nss_pa8: spi2_nss_pa8 {
   };

   /omit-if-no-ref/ spi2_nss_pb9: spi2_nss_pb9 {
   };

   /omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
   };

   /omit-if-no-ref/ spi2_nss_pd0: spi2_nss_pd0 {
   };

   /omit-if-no-ref/ spi3_nss_pa4: spi3_nss_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi1_sck_pa1: spi1_sck_pa1 {
   };

   /omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
   };

   /omit-if-no-ref/ spi1_sck_pb3: spi1_sck_pb3 {
   };

   /omit-if-no-ref/ spi1_sck_pd8: spi1_sck_pd8 {
   };

   /omit-if-no-ref/ spi2_sck_pa0: spi2_sck_pa0 {
   };

   /omit-if-no-ref/ spi2_sck_pb8: spi2_sck_pb8 {
   };

   /omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
   };

   /omit-if-no-ref/ spi2_sck_pb13: spi2_sck_pb13 {
   };

   /omit-if-no-ref/ spi2_sck_pd1: spi2_sck_pd1 {
   };

   /omit-if-no-ref/ spi3_sck_pb3: spi3_sck_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch2n_pb0: tim1_ch2n_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch2_pb3: tim1_ch2_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch3_pb6: tim1_ch3_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch1n_pb13: tim1_ch1n_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch2n_pb14: tim1_ch2n_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch3n_pb15: tim1_ch3n_pb15 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch1_pc8: tim1_ch1_pc8 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch2_pc9: tim1_ch2_pc9 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch3_pc10: tim1_ch3_pc10 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch4_pc11: tim1_ch4_pc11 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch1n_pd2: tim1_ch1n_pd2 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch2n_pd3: tim1_ch2n_pd3 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim1_ch3n_pd4: tim1_ch3n_pd4 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch4_pa3: tim2_ch4_pa3 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch2_pb3: tim2_ch2_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch1_pc4: tim2_ch1_pc4 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch2_pc5: tim2_ch2_pc5 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch3_pc6: tim2_ch3_pc6 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim2_ch4_pc7: tim2_ch4_pc7 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch3_pb0: tim3_ch3_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim14_ch1_pa4: tim14_ch1_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim14_ch1_pb1: tim14_ch1_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim4_ch1_pb6: tim4_ch1_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim4_ch2_pb7: tim4_ch2_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim4_ch3_pb8: tim4_ch3_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim4_ch4_pb9: tim4_ch4_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim14_ch1_pc12: tim14_ch1_pc12 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim14_ch1_pf0: tim14_ch1_pf0 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch2_pa3: tim15_ch2_pa3 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1n_pb13: tim15_ch1n_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1_pb14: tim15_ch1_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1n_pb15: tim15_ch1n_pb15 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch2_pb15: tim15_ch2_pb15 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1_pc1: tim15_ch1_pc1 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch2_pc2: tim15_ch2_pc2 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim15_ch1n_pf1: tim15_ch1n_pf1 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim16_ch1_pa6: tim16_ch1_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim16_ch1n_pb6: tim16_ch1n_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim16_ch1_pb8: tim16_ch1_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim16_ch1_pd0: tim16_ch1_pd0 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim17_ch1_pa7: tim17_ch1_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim17_ch1n_pb7: tim17_ch1n_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim17_ch1_pb9: tim17_ch1_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ tim17_ch1_pd1: tim17_ch1_pd1 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_cts_pa6: lpuart1_cts_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_cts_pb4: usart1_cts_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_cts_pb13: lpuart1_cts_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_cts_pb0: lpuart2_cts_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_cts_pc8: lpuart2_cts_pc8 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_cts_pd3: usart2_cts_pd3 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_cts_pa6: usart3_cts_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_cts_pb13: usart3_cts_pb13 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart4_cts_pb7: usart4_cts_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_cts_pb6: usart5_cts_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_cts_pd5: usart5_cts_pd5 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_cts_pa6: usart6_cts_pa6 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_cts_pb15: usart6_cts_pb15 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_de_pa12: usart1_de_pa12 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
    drive-push-pull;
   };

   /omit-if-no-ref/ lpuart1_de_pb1: lpuart1_de_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_de_pb3: usart1_de_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_de_pb12: lpuart1_de_pb12 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_de_pa1: usart2_de_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_de_pb1: lpuart2_de_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_de_pc9: lpuart2_de_pc9 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_de_pd4: usart2_de_pd4 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_de_pf2: lpuart2_de_pf2 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_de_pa15: usart3_de_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_de_pb1: usart3_de_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_de_pb14: usart3_de_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_de_pd2: usart3_de_pd2 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart4_de_pa15: usart4_de_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_de_pb5: usart5_de_pb5 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_de_pd4: usart5_de_pd4 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_de_pa7: usart6_de_pa7 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_de_pb14: usart6_de_pb14 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
   };

   /omit-if-no-ref/ lpuart1_rts_pb1: lpuart1_rts_pb1 {
   };

   /omit-if-no-ref/ usart1_rts_pb3: usart1_rts_pb3 {
   };

   /omit-if-no-ref/ lpuart1_rts_pb12: lpuart1_rts_pb12 {
   };

   /omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
   };

   /omit-if-no-ref/ lpuart2_rts_pb1: lpuart2_rts_pb1 {
   };

   /omit-if-no-ref/ lpuart2_rts_pc9: lpuart2_rts_pc9 {
   };

   /omit-if-no-ref/ usart2_rts_pd4: usart2_rts_pd4 {
   };

   /omit-if-no-ref/ lpuart2_rts_pf2: lpuart2_rts_pf2 {
   };

   /omit-if-no-ref/ usart3_rts_pa15: usart3_rts_pa15 {
   };

   /omit-if-no-ref/ usart3_rts_pb1: usart3_rts_pb1 {
   };

   /omit-if-no-ref/ usart3_rts_pb14: usart3_rts_pb14 {
   };

   /omit-if-no-ref/ usart3_rts_pd2: usart3_rts_pd2 {
   };

   /omit-if-no-ref/ usart4_rts_pa15: usart4_rts_pa15 {
   };

   /omit-if-no-ref/ usart5_rts_pb5: usart5_rts_pb5 {
   };

   /omit-if-no-ref/ usart5_rts_pd4: usart5_rts_pd4 {
   };

   /omit-if-no-ref/ usart6_rts_pa7: usart6_rts_pa7 {
   };

   /omit-if-no-ref/ usart6_rts_pb14: usart6_rts_pb14 {
   };

   /omit-if-no-ref/ lpuart1_rx_pa3: lpuart1_rx_pa3 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_rx_pb7: usart1_rx_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_rx_pb10: lpuart1_rx_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_rx_pc0: lpuart1_rx_pc0 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_rx_pc5: usart1_rx_pc5 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_rx_pa3: usart2_rx_pa3 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_rx_pa13: lpuart2_rx_pa13 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_rx_pa15: usart2_rx_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_rx_pb7: lpuart2_rx_pb7 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_rx_pc1: lpuart2_rx_pc1 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_rx_pc7: lpuart2_rx_pc7 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_rx_pd6: usart2_rx_pd6 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_rx_pb0: usart3_rx_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_rx_pb9: usart3_rx_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_rx_pc5: usart3_rx_pc5 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart4_rx_pa1: usart4_rx_pa1 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart4_rx_pc11: usart4_rx_pc11 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_rx_pb1: usart5_rx_pb1 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_rx_pb4: usart5_rx_pb4 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_rx_pd2: usart5_rx_pd2 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_rx_pa5: usart6_rx_pa5 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_rx_pb9: usart6_rx_pb9 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_rx_pc1: usart6_rx_pc1 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_tx_pa2: lpuart1_tx_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_tx_pb6: usart1_tx_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_tx_pb11: lpuart1_tx_pb11 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart1_tx_pc1: lpuart1_tx_pc1 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart1_tx_pc4: usart1_tx_pc4 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_tx_pa14: lpuart2_tx_pa14 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_tx_pa14: usart2_tx_pa14 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_tx_pb6: lpuart2_tx_pb6 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_tx_pc0: lpuart2_tx_pc0 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_tx_pc6: lpuart2_tx_pc6 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ lpuart2_tx_pf2: lpuart2_tx_pf2 {
    pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pa5: usart3_tx_pa5 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pb2: usart3_tx_pb2 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pb8: usart3_tx_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pc4: usart3_tx_pc4 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart4_tx_pa0: usart4_tx_pa0 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart4_tx_pc10: usart4_tx_pc10 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_tx_pb0: usart5_tx_pb0 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_tx_pb3: usart5_tx_pb3 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_tx_pc12: usart5_tx_pc12 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart5_tx_pd3: usart5_tx_pd3 {
    pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_tx_pa4: usart6_tx_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_tx_pb8: usart6_tx_pb8 {
    pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usart6_tx_pc0: usart6_tx_pc0 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ ucpd1_cc1_pa8: ucpd1_cc1_pa8 {
   };

   /omit-if-no-ref/ ucpd1_cc2_pb15: ucpd1_cc2_pb15 {
   };

   /omit-if-no-ref/ ucpd2_cc1_pd0: ucpd2_cc1_pd0 {
   };

   /omit-if-no-ref/ ucpd2_cc2_pd2: ucpd2_cc2_pd2 {
   };

   /omit-if-no-ref/ usb_noe_pa4: usb_noe_pa4 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usb_dm_pa11: usb_dm_pa11 {
   };

   /omit-if-no-ref/ usb_dp_pa12: usb_dp_pa12 {
   };

   /omit-if-no-ref/ usb_noe_pa13: usb_noe_pa13 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usb_noe_pa15: usb_noe_pa15 {
    pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

   /omit-if-no-ref/ usb_noe_pc9: usb_noe_pc9 {
    pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
   };

  };
 };
};
# 10 "C:/Users/iteedi/zephyrproject/projects/EWS/firmware/canfd_cdc_composite/boards/arm/ews/ews.dts" 2
# 1 "C:/Users/iteedi/zephyrproject/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h" 1 3 4
# 11 "C:/Users/iteedi/zephyrproject/projects/EWS/firmware/canfd_cdc_composite/boards/arm/ews/ews.dts" 2

/ {
    model = "EWS STM32G0B1KBU6 board";
    compatible = "st,stm32g0b1kb-ews";

    chosen {
        zephyr,console = &usart1;
        zephyr,shell-uart = &usart1;
        zephyr,uart-mcumgr = &usart1;
        zephyr,sram = &sram0;
        zephyr,flash = &flash0;
        zephyr,code-partition = &slot0_partition;
        zephyr,canbus = &fdcan2;
    };

    leds: leds {
        compatible = "gpio-leds";
        status_led: led_0 {
            gpios = <&gpiob 4 (0 << 0)>;
            label = "Status LED";
        };
    };

    gpio_keys {
        compatible = "gpio-keys";
        pfet1: pfet1 {
            label = "PFET1";
            gpios = <&gpioa 8 (0 << 0)>;
            zephyr,code = <2>;
        };
        pfet2: pfet2 {
            label = "PFET2";
            gpios = <&gpiob 2 (0 << 0)>;
            zephyr,code = <3>;
        };
    };

    aliases {
        led0 = &status_led;
        pfet0 = &pfet1;
        pfet1 = &pfet2;
        watchdog0 = &iwdg;
        die-temp0 = &die_temp;
        volt-sensor0 = &vref;
        volt-sensor1 = &vbat;
    };
};

&clk_lsi {
    status = "okay";
};

&clk_hsi {
};

&clk_hsi48 {
    crs-usb-sof;
};

&pll {
    div-m = <1>;
    mul-n = <8>;
    div-p = <2>;
    div-q = <2>;
    div-r = <2>;
    clocks = <&clk_hsi>;
};

&rcc {
    clocks = <&pll>;
    clock-frequency = <(((64) * 1000) * 1000)>;
    ahb-prescaler = <1>;
    apb1-prescaler = <1>;
};

zephyr_udc0: &usb {
    pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
    pinctrl-names = "default";
};

&usart1 {
    pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
    current-speed = <115200>;
};

&rtc {
    clocks = <&rcc (0x03c) (1 << 10)>,
             <&rcc 0x003 ((((0x5C) & 0xFFFFU) << 0U) | (((8) & 0x1FU) << 16U) | ((((9) - (8)) & 0x3U) << 21U) | ((((2)) & 0xFFU) << 24U))>;
};

&iwdg {
};

&fdcan2 {
    clocks = <&rcc (0x03c) (1 << 12)>,
             <&rcc ((((((((0x003 + 1) + 1) + 1) + 1) + 1) + 1) + 1) + 1) ((((0x58) & 0xFFFFU) << 0U) | (((8) & 0x1FU) << 16U) | ((((9) - (8)) & 0x3U) << 21U) | ((((1)) & 0xFFU) << 24U))>;
    pinctrl-0 = <&fdcan2_rx_pb0 &fdcan2_tx_pb1>;
};

&die_temp {
};

&vref {
};

&vbat {
};

&flash0 {
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        boot_partition: partition@0 {
            label = "mcuboot";
            reg = <0x00000000 ((16) * 1024)>;
            read-only;
        };

        slot0_partition: partition@4000 {
            label = "image-0";
            reg = <0x00004000 ((96) * 1024)>;
        };

        slot1_partition: partition@1c000 {
            label = "image-1";
            reg = <0x0001c000 ((16) * 1024)>;
        };
    };
};

stm32_lp_tick_source: &lptim1 {
    clocks = <&rcc (0x03c) (1 << 31)>,
             <&rcc 0x003 ((((0x54) & 0xFFFFU) << 0U) | (((18) & 0x1FU) << 16U) | ((((19) - (18)) & 0x3U) << 21U) | ((((1)) & 0xFFU) << 24U))>;
};
# 0 "<command-line>" 2
# 1 "C:/Users/iteedi/zephyrproject/zephyr/misc/empty_file.c"

Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).

The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.

For details, see "2.3.6 reg" in Devicetree Specification v0.4.

Indicates the operational status of the hardware or other
resource that the node represents. In particular:

  - "okay" means the resource is operational and, for example,
    can be used by device drivers
  - "disabled" means the resource is not operational and the system
    should treat it as if it is not present

For details, see "2.3.4 status" in Devicetree Specification v0.4.

This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.

The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.

The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.

For details, see "2.3.1 compatible" in Devicetree Specification v0.4.

Optional names given to each register block in the "reg" property.
For example:

  / {
       soc {
           #address-cells = <1>;
           #size-cells = <1>;

           uart@1000 {
               reg = <0x1000 0x2000>, <0x3000 0x4000>;
               reg-names = "foo", "bar";
           };
       };
  };

The uart@1000 node has two register blocks:

  - one with base address 0x1000, size 0x2000, and name "foo"
  - another with base address 0x3000, size 0x4000, and name "bar"

Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.

Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.

If present, this refers to the node which handles interrupts generated
by this device.

Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.

For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.

Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:

  https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

Optional names given to each clock provider in the "clocks" property.

This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree

This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.

Optional names given to the DMA channel specifiers in the "dmas" property.

Optional names given to the IO channel specifiers in the "io-channels" property.

Optional names given to the mbox specifiers in the "mboxes" property.

Optional names given to the power domain specifiers in the "power-domains" property.

Optional names given to the hwlock specifiers in the "hwlocks" property.

Do not initialize device automatically on boot. Device should be manually
initialized using device_init().

Property to identify that a device can be used as wake up source.

When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.

Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.

Automatically configure the device for runtime power management after the
init function runs.

This property provides a byte which should used to enable non-permanent
readout protection (RDP1). Actually, any byte except 0xAA and 0xCC
(which are used by RDP0 and RDP2 respectively) can be used to enable
RDP1 but in multi-image environment, some other image could check if
RDP1 is enabled by comparing it to some hardcoded value. The byte has to
be different than 0xAA and 0xCC.

STM32F0/G0 RCC (Reset and Clock controller).

For more description confere st,stm32-rcc.yaml

AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.

On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.

STM32G0 main PLL.

It can take one of clk_hse or clk_hsi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP  --> to I2S
  f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
  f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed 64 MHz.

PLL division factor for PLLCLK (system clock)
Valid range: 2 - 8

STM32G0 HSI Clock.

On STM32G0, HSI is a 16MHz fixed clock.

It also produces a HSISYS secondary clk which can be used as system clock
source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
SYSCLK = HSI16 / HSI DIV
      enum:
      - 1 ==> HSISYS = 16MHZ
      - 2 ==> HSISYS = 8MHZ
      - 4 ==> HSISYS = 4MHZ
      - 8 ==> HSISYS = 2MHZ
      - 16 ==> HSISYS = 1MHZ
      - 32 ==> HSISYS = 0.5MHz
      - 64 ==> HSISYS = 0.25MHZ
      - 128 ==> HSISYS = 0.125MHz

HSI clock divider. Configures the output HSI clock frequency (HSISYS),
It does not apply to HSI clk selected as peripheral source clock
(eg: RNG clk driven by HSI)

STM32 flash memory.

This binding is for the flash memory itself, not the flash controller peripheral.
For that, see the "st,stm32-flash-controller" binding.

max erase time(millisecond) of a flash sector or page or half-page

Embedded flash memory bank 2 size in KBytes.
Used by CM4 CPU because it cannot access flash controller register to read size.
Provides a way to configure this size when the flash controller driver runs on CM4 CPU.

Fixed partitions of a flash (or other non-volatile storage) memory.

Here is an example:

  &flash0 {
          partitions {
                  compatible = "fixed-partitions";
                  #address-cells = <1>;
                  #size-cells = <1>;

                  boot_partition: partition@0 {
                          label = "mcuboot";
                          reg = <0x00000000 0x0000C000>;
                  };
                  slot0_partition: partition@c000 {
                          label = "image-0";
                          reg = <0x0000C000 0x00076000>;
                  };
                  slot1_partition: partition@82000 {
                          label = "image-1";
                          reg = <0x00082000 0x00076000>;
                  };

                  /*
                   * The flash starting at 0x000f8000 and ending at
                   * 0x000fffff is reserved for use by the application.
                   */

                  /*
                   * Storage partition will be used by FCB/LittleFS/NVS
                   * if enabled.
                   */
                  storage_partition: partition@f8000 {
                          label = "storage";
                          reg = <0x000f8000 0x00008000>;
                  };
          };
  };

Note that the usual name for this node is 'partitions'.
The fixed-partitions node should be a child of the flash
memory node. Note also that the flash memory node is usually
different from the node representing the flash controller
IP block.

Above, slot0_partition's register address 0xc000 means that
the partition begins at that offset from the parent flash
memory flash0's base address. That is, partition addresses
are relative; physical addresses must be calculated by adding
the start address of flash0 in memory to each partition's
reg address.

Number of cells required to represent a child node's
reg property address. This must be large enough to
represent the start offset of each partition.

represent the size of each partition in bytes.

Each child node of the fixed-partitions node represents
an individual flash partition. These should usually
look like this:

  partition_nodelabel: partition@START_OFFSET {
          label = "human-readable-name";
          reg = <0xSTART_OFFSET 0xSIZE>;
  };

This should be in the format <OFFSET SIZE>, where OFFSET
is the offset of the flash partition relative to the base
address of the parent memory, and SIZE is the size of
the partition in bytes.

STM32 Reset and Clock Control (RCC) Controller.

This node is in charge of reset control for AHB (Advanced High Performance)
and APB (Advanced Peripheral) bus domains.

To specify the reset line in a peripheral, the standard resets property needs
to be used, e.g.:

  usart1: serial@xxx {
      ...
      /* Cell contains information about RCU register offset and bit */
      resets = <&rctl STM32_RESET(ABP2, 4)>;
      ...
  };

RCC reset cells are available in
include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.

Number of cells in reset property. There must be a cell
named "id" to use the reset_dt_spec macros.

Indicates if the driver should set bit in clear register to
deassert reset.

STM32G0 External Interrupt Controller

This compatible stands for all interrupt-controller blocks with two
dedicated Rising and Falling interrupt pending registers.

Total number of EXTI lines dedicated to GPIO interrupts.
The default value of 16 mirrors hardware of most STM32 devices.

Description of the input lines range for each interrupt line supported
by the external interrupt controller. For each line a couple of integers is
provided: the number of the first line of the range start and the length
of the range.
As example:
       line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
                     <4 1>, <5 5>, <10 6>;
Above property provides event-range for 7 lines.
5 first lines contain one element
6th line starts with input line 5 and contains 5 elements (5 to 9)
7th line starts with inupt line 10 and contains 6 elements (10 to 15)

STM32 Pin controller.

Based on pincfg-node.yaml binding.

Note: `bias-disable` and `drive-push-pull` are default pin configurations.
       They will be applied in case no `bias-foo` or `driver-bar` properties
       are set.

Remaps the PA11 pin to operate as PA9 pin. Use of this property is restricted to STM32G0 and STM32C0 SoCs.

Remaps the PA12 pin to operate as PA10 pin. Use of this property is restricted to STM32G0 and STM32C0 SoCs.

Remaps the PA11/PA12 pin to operate as PA9/PA10 pin. Use of this property is restricted to STM32F070x SoCs.

This binding gives a base representation of the STM32 pins configuration

Reused from
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
Integer represents gpio pin number and mux setting.
Each integer encodes a port, line and alternate function.
With:
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
- function: The function number, can be:
* 0 : Alternate Function 0
* 1 : Alternate Function 1
* 2 : Alternate Function 2
* ...
* 15 : Alternate Function 15
* 16 : Analog
* 17 : GPIO
In case selected pin function is GPIO, pin is statically configured as
a plain input/output GPIO. Default configuration is input. Output value
can be configured by adding 'ouptut-low' or 'output-high' properties
to the pin configuration.

To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
  -include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h
Some examples of macro usage:
   GPIO A9 set as alternate function 2
... {
         pinmux = <STM32_PINMUX('A', 9, AF2)>;
};
   GPIO A9 set as analog
... {
         pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
   GPIO A9 set as GPIO output high
... {
         pinmux = <STM32_PINMUX('A', 9, GPIO)>;
         output-high;
};

Pin speed. Default to low-speed. For few pins (PA11 and
PB3 depending on SoCs)hardware reset value could differ
(very-high-speed). Carefully check reference manual for these pins.

This property indicates the number of in-use slots of available slots
for GPIOs. The STM32 GPIO controller typically has all 16 possible port
IO with few exceptions. It should only be necessary to explicitly set
this property if the controller itself does not implement all 16 port
IO register bits; for example PORTE in the STM32WB55xx series which only
implements the first 5. Package restrictions on the number of exposed
GPIO should not influence this property. For cases in which there might
be holes in the slot range, this value should be the max slot number+1.

If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
this property contains an additional set of tuples which specify which GPIOs
are unusable. This property indicates the start and size of the GPIOs
that can't be used.

For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.

This is an array of strings defining the names of the GPIO lines
going out of the GPIO controller

Optional GPIO hog configuration.

Each GPIO controller may contain GPIO hog definitions. GPIO hogging is a mechanism for
providing automatic GPIO configuration during driver initialization when Kconfig
CONFIG_GPIO_HOGS is enabled.

Each GPIO hog is represented as a child node of the GPIO controller.

Example:
  &gpio1 {
    mux-hog {
      gpio-hog;
      gpios = <10 GPIO_ACTIVE_HIGH>, <11 GPIO_ACTIVE_HIGH>;
      output-high;
    };
  };

  &gpio2 {
    test-hog {
      gpio-hog;
      gpios = <26 GPIO_ACTIVE_HIGH>;
      output-low;
      line-name = "test";
  };
};

This is an array of GPIO specifiers (e.g. pin, flags) to be hogged. The number of array
entries must be an integer multiple of the number of GPIO specifier cells for the parent
GPIO controller.

If this property is set, the GPIO is configured as an input. This property takes
precedence over the output-low and output-high properties.

If this property is set, the GPIO is configured as an output set to logical low. This
property takes precedence over the output-high property.

If this property is set, the GPIO is configured as an output set to logical high.

RTC synchronous prescaler value. Optional, if not set defaulted in code to:
- Selected to give 1 Hz tick rate, based on source clock frequency and asynchronous
  prescaler value.

RTC asynchronous prescaler value. Optional, if not set defaulted in code to:
- 0x7F if RTC source clock is LSE/LSI
- 1 if using counter with CONFIG_COUNTER_RTC_STM32_SUBSECONDS option
- 0x7C if RTC source clock is HSE

RTC HSE prescaler value. Applies only when RTC source clock is HSE.
Optional, defaulting to the value calculated based on HSE clock frequency
to give the highest possibly prescaled source frequency below 1MHz.

Number of alarms supported by STM32 RTC device.
Most of STM32 MCU series have 2 RTC alarms, A & B.
Defaults to 0 when not declared in devicetree.

Number of the Extended Interrupts and Event Controller (EXTI) interrupt
line connected to the RTC Alarm event.
Not required, since RTC Alarm interrupt could be routed directly to Nested
Vectored Interrupt Controller (NVIC) and to Power Control (PWR) wake-up
pins on some series.
Valid range: 0 - 31

RTC frequency equals clock-frequency divided by the prescaler value

STM32 Battery Backed RAM

STM32 BBRAM are 32-bit registers which can be used for storing user
application data. They are implemented in the backup domain that remains
powered-on by VBAT when the VDD power is switched off. They are not reset
by system reset or when the device wakes up from Standby mode. They are
reset by a backup domain reset.

Note: Since STM32 BBRAM is in RTC backup domain, STM32 RTC node must be
      enabled if STM32 BBRAM node is enabled.

Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.

Sets the number of stop bits. Defaults to standard of 1 if not specified.

Sets the number of data bits. Defaults to standard of 8 if not specified.

Enable the single wire half-duplex communication.
Using this mode, TX and RX lines are internally connected and
only TX pin is used afterwards and should be configured.
RX/TX conflicts must be handled on user side.

Swap the TX and RX pins. Used in case of a cross wired connection.

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

Names for the provided states. The number of names needs to match the
number of states.

EXTI line number matching the device wakeup interrupt mask register.
This property is required on stm32 devices where the wakeup interrupt signal could be
configured masked at boot (sm32wl55 for instance), preventing the device to wakeup
the core from stop mode(s).

Enable activating an external transeiver through the DE pin which must also be configured
using pinctrl.

Defines the time between the activation of the DE signal and the beginning of the start bit.
It is expressed in 16th of a bit time.

Defines the time between the end of the stop bit and the deactivation of the DE signal.

Invert the binary logic of the de pin. When enabled, physical logic levels are inverted and
we use 1=Low, 0=High instead of 1=High, 0=Low.

Enables transmit and receive FIFO using default FIFO configuration (typically threshold is
set to 1/8).
In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also
allows more reliable communication with UART devices sensitive to variation of inter-frames
delays.
In RX, FIFO reduces overrun occurrences.

Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity, 3 for mark parity and 4 for space parity.
Default to none if not specified.

Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and

Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and

STM32 low-power timer (LPTIM).

The lptim node to be used for counting ticks during lowpower modes
must be named stm32_lp_tick_source in the DTS, as follows:
 status = "okay";
}

Clock divider at the input of the lptimer clock, default reset value is 'not divided'.

Prescaler allows to achieve higher LPTIM timeout (up to 256s when lptim clocked by LSE)
and consequently higher core sleep durations, but impacts the tick precision.
To be used with caution.
CONFIG_SYS_CLOCK_TICKS_PER_SEC could be used to tune tick duration and gain precision,
at kernel timing granularity cost.

For example, when LPTIM is clocked by the LSE (32768Hz) and st,prescaler = <32>:
LPTIM global timeout is 64 seconds with an increment of 0.97 ms.
Using CONFIG_SYS_CLOCK_TICKS_PER_SEC = 4096, tick = 0.24 ms, LPTIM precision is 4 ticks.
Using CONFIG_SYS_CLOCK_TICKS_PER_SEC = 1024, tick = 0.97 ms, LPTIM precision is 1 ticks.

Gives the LPTIM an exact counting value (s) for timeout expiration.
Valid range is [1, 256] and should be consistent with st,prescaler
pre-defined setting. If not, an error is raised.

Clock prescaler at the input of the timer
Could be in range [0 .. 0xFFFF] for STM32 General Purpose Timers (CLK/(prescaler+1) )

Sets timer counter mode.

Use constants defined in dt-bindings/timer/stm32-timer.h.

* STM32_TIM_COUNTERMODE_UP             - used as upcounter.
* STM32_TIM_COUNTERMODE_DOWN           - used as downcounter.
* STM32_TIM_COUNTERMODE_CENTER_DOWN    - counts up and down alternatively.
                                         Output compare interrupt flags of output channels
                                         are set only when the counter is counting down.
* STM32_TIM_COUNTERMODE_CENTER_UP      - counts up and down alternatively.
                                         are set only when the counter is counting up.
* STM32_TIM_COUNTERMODE_CENTER_UP_DOWN - counts up and down alternatively.
                                         are set only when the counter is counting up or
                                         down.

If absent, then STM32_TIM_COUNTERMODE_UP is used (reset state).

Add support to capture on four channels. This is less accurate than
the default 2 channel support because the counter is reset by
interrupt instead of slave-mode controller. This option can also
be used as alternative for timers that does not support slave mode.

Number of items to expect in a PWM
- channel of the timer used for PWM
- period to set in ns
- flags : combination of standard flags like PWM_POLARITY_NORMAL
  or specific flags like STM32_PWM_COMPLEMENTARY. As an example,
  the following complementary PWMs(CH2&CH2N) are shown below.
    <&pwm1 2 100 (PWM_POLARITY_NORMAL)>;
    <&pwm1 2 100 (PWM_POLARITY_NORMAL | STM32_PWM_COMPLEMENTARY)>;

Set encoder mode.
The following modes are supported:
0x1: Encoder mode 1 (Default)
0x2: Encoder mode 2
0x3: Encoder mode 3
Some MCUs supports additional modes:
0x10002: Encoder mode: Clock plus direction, x2 mode
0x10003: Encoder mode: Clock plus direction, x1 mode
0x10004: Encoder mode: Directional Clock, x2 mode
0x10005: Encoder mode: Directional Clock, x1 mode
0x10006: Quadrature encoder mode: x1 mode, counting on tim_ti1fp1
0x10007: Quadrature encoder mode: x1 mode, counting on tim_ti2fp2
Default value complies with stm32 low level timer encoder init value.

Intensity of the filter applied to the input signal. This is
implemented by scaling the sampling frequency and adding a counter
in which N consecutive samples with same value are needed to validate
a transition.
Mapping is as follows (F_clk is the timer's clock):
0: No filter, sampling is done at F_dts (default value)
1: Fs = F_clk, N=2
2: Fs = F_clk, N=4
3: Fs = F_clk, N=8
4: Fs = F_clk/2, N=6
5: Fs = F_clk/2, N=8
6: Fs = F_clk/4, N=6
7: Fs = F_clk/4, N=8
8: Fs = F_clk/8, N=6
9: Fs = F_clk/8, N=8
10: Fs = F_clk/16, N=5
11: Fs = F_clk/16, N=6
12: Fs = F_clk/16, N=8
13: Fs = F_clk/32, N=5
14: Fs = F_clk/32, N=6
15: Fs = F_clk/32, N=8
Default value is set by hardware at reset

This is a number >= 1 that is used to determine how many revolutions
were done based on the current counter's value.

Human readable string describing the sensor. It can be used to
distinguish multiple instances of the same model (e.g., lid accelerometer
vs. base accelerometer in a laptop) to a host operating system.

This property is defined in the Generic Sensor Property Usages of the HID
Usage Tables specification
(https://usb.org/sites/default/files/hut1_3_0.pdf, section 22.5).

An optional table of pre-computed i2c timing values with the
matching clock configuration.

Precise timings values for a given Hardware can be pre-computed
with a tool like STM32CubeMX or directly from I2C_TIMINGR register
description.

Because timing value is valid for a given I2C peripheral clock
frequency and target I2C bus clock, each timing value must be
provided with the matching configuration.

The resulting table entries should look like <periph_clock
clock-frequency timing>

For example timings could be defined as

    timings = <64000000 I2C_BITRATE_STANDARD 0x10707DBC>,
              <64000000 I2C_BITRATE_FAST 0x00603D56>,
              <56000000 I2C_BITRATE_STANDARD 0x10606DA4>,
              <56000000 I2C_BITRATE_FAST 0x00501D63>;

GPIO to which the I2C SCL signal is routed. This is only needed for
I2C bus recovery support.

GPIO to which the I2C SDA signal is routed. This is only needed for

Optional DMA channels used by the I2C peripheral. If specified, these
channels can be used to handle RX and TX transactions over DMA.

Names of the optional DMA channels. Expected values are "tx" for
the TX channel and "rx" for the RX channel.

An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.

Expected names are the following:
- "adcx" for the enabling the register clock (mandatory)
- "adc_ker" for configuring the kernel clock (if applicable)
- "adc_pre" for configuring the prescaler (if applicable)
Kernel clock and prescaler may be shared between several ADC instances.
In that case, the same kernel clock/prescaler Device Tree configuration
must be used on all instances that share the kernel clock/prescaler
to avoid conflicts.

Type of ADC clock source :
- "SYNC": derived from the bus clock.
- "ASYNC" : independent and asynchronous with the bus clock
One of the two values may not apply to some series. Refer to the RefMan.
If an asynchronous clock is selected, a kernel clock in the "clocks" property
has to be defined explicitly.

Clock prescaler at the input of the ADC:
Apply to synchronous or asynchronous clock depending on the STM32
st,adc-clock-source.
Some of the values may not apply to some series, and may depend on the
selected clock source. Refer to the RefMan.
On STM32F3x, this configures only the synchronous prescaler
(use the "clocks" property to set asynchronous prescaler).

Indicates the reference voltage of the ADC in mV (on the target board).

List of the resolutions supported by the ADC instance. They should be
values created with STM32_ADC_RES macro or similar. Their order is not
important. For example for STM32F4:
  <STM32_ADC_RES(12, 0x00) STM32_ADC_RES(10, 0x01)
   STM32_ADC_RES(8, 0x02)  STM32_ADC_RES(6, 0x03)>
The two parameters are the resolution (for example 10 bits) and the
corresponding register value (0x01 for a 10-bit resolution).
By design, these macros also contains all register information (address,
field offset and field mask) necessary to properly set the resolution.

List all the sampling times supported by the ADC instance.
Rounded up if needed. Order is important: their index matches their binary
value in the register.

Number of sampling time common channels for this ADC instance, if any.

Type of ADC sequencer:
- "fixed": Channels of a sequence are sampled from lowest to highest.
- "programmable": Channels of a sequence can be sampled in any order.

Type of ADC oversampler:
- "none": No oversampler
- "minimal": Oversampler with 8 possible oversampling values (2, 4, 8, ..., 256)
- "extended": Oversampler with 1024 possible oversampling values (1..1024)

Presence and type of ADC internal regulator if any.
- "none": No internal regulator.
- "startup-sw-delay": Internal regulator is present and its startup time is checked with a
  software delay.
- "startup-hw-status": Internal regulator is present and its startup time is checked with a
  status flag in a register.

If present, it indicates that the ADC instance has a deep power down feature.

If present, it indicates that the ADC instance has a channel preselection register.

If present, it indicates that the ADC instance supports differential channel inputs.

Channel configuration.

All nodes using this binding must be named "channel", otherwise their
data will not be accessible for the ADC API macros.

This is based on Linux, documentation:
  https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/adc/adc.yaml

Gain selection:
- ADC_GAIN_1_6: x 1/6
- ADC_GAIN_1_5: x 1/5
- ADC_GAIN_1_4: x 1/4
- ADC_GAIN_2_7: x 2/7
- ADC_GAIN_1_3: x 1/3
- ADC_GAIN_2_5: x 2/5
- ADC_GAIN_1_2: x 1/2
- ADC_GAIN_2_3: x 2/3
- ADC_GAIN_4_5: x 4/5
- ADC_GAIN_1:   x 1
- ADC_GAIN_2:   x 2
- ADC_GAIN_3:   x 3
- ADC_GAIN_4:   x 4
- ADC_GAIN_6:   x 6
- ADC_GAIN_8:   x 8
- ADC_GAIN_12:  x 12
- ADC_GAIN_16:  x 16
- ADC_GAIN_24:  x 24
- ADC_GAIN_32:  x 32
- ADC_GAIN_64:  x 64
- ADC_GAIN_128: x 128

Reference selection:
- ADC_REF_VDD_1:     VDD
- ADC_REF_VDD_1_2:   VDD/2
- ADC_REF_VDD_1_3:   VDD/3
- ADC_REF_VDD_1_4:   VDD/4
- ADC_REF_INTERNAL:  Internal
- ADC_REF_EXTERNAL0: External, input 0
- ADC_REF_EXTERNAL1: External, input 1

This property can be used to specify the voltage (in millivolts)
of the reference selected for this channel, so that applications
can get that value if needed for some calculations.
For the internal reference, the voltage can be usually obtained with
a dedicated ADC API call, so there is no need to use this property
in that case, but for other references this property can be useful.

Acquisition time.
Use the ADC_ACQ_TIME macro to compose the value for this property
or pass ADC_ACQ_TIME_DEFAULT to use the default setting for a given
hardware (e.g. when the hardware does not allow to configure the
acquisition time).

When set, selects differential input mode for the channel. Otherwise,
single-ended mode is used unless the zephyr,input-negative property is
specified, in which case the differential mode is selected implicitly.

Positive ADC input. Used only for drivers that select
the ADC_CONFIGURABLE_INPUTS Kconfig option.

Negative ADC input. Used only for drivers that select
When specified, implies the differential input mode for the channel.

Oversampling setting to be used for the channel.
When specified, each sample is averaged from 2^N conversion results
(where N is the provided value).

Output pin selection for the current sources. The actual
interpretation depends on the driver. This is used only for drivers
which select the ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN
Kconfig option.

Output pin selection for the bias voltage. The actual interpretation
depends on the driver. This is used only for drivers which select
the ADC_CONFIGURABLE_VBIAS_PIN Kconfig option.

STM32 DMA controller (V2)

It is present on stm32 devices like stm32L4 or stm32WB.
This DMA controller includes several channels with different requests.
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a four-cell specifier for each
capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
described in the dma.txt file, using a 3-cell specifier for each
channel: a phandle to the DMA controller plus the following four integer cells:
  1. channel: the dma stream from 1 to <dma-requests>
  2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
  this value is 0 for Memory-to-memory transfers
  or a value between <1> .. <dma-generators> (not supported yet)
  or a value between <dma-generators>+1  ..  <dma-generators>+<dma-requests>
  3. channel-config: A 32bit mask specifying the DMA channel configuration
  A name custom DMA flags for channel configuration is used
  which is device dependent. See stm32_dma.h:
    -bit 5 : DMA  cyclic mode config
              0x0: STM32_DMA_MODE_NORMAL
              0x1: STM32_DMA_MODE_CYCLIC
    -bit 6-7 : Direction (see dma.h)
              0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
              0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
              0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
              0x3: reserved for PERIPH to PERIPH
    -bit 9 : Peripheral Increment Address
             0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
             0x1: STM32_DMA_PERIPH_INC: increment address between transfers
    -bit 10 : Memory Increment Address
             0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
             0x1: STM32_DMA_MEM_INC: increment address between transfers
    -bit 11-12 : Peripheral data size
             0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
             0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
             0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
             0x3: reserved
    -bit 13-14 : Memory data size
             0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
             0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
             0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
    -bit 15: Reserved
    -bit 16-17 : Priority level
             0x0: STM32_DMA_PRIORITY_LOW: low
             0x1: STM32_DMA_PRIORITY_MEDIUM: medium
             0x2: STM32_DMA_PRIORITY_HIGH: high
             0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high

Example of dma usual combination for peripheral transfer
     #define STM32_DMA_PERIPH_TX	(STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
     #define STM32_DMA_PERIPH_RX	(STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)

Example of dma node for stm32wb55x
   dma2: dma-controller@40020400 {
       compatible = "st,stm32-dma-v2";
       ...
       dma-requests = <7>;
       status = "disabled";
      };

For the client part, example for stm32l476 on DMA1 instance
  Tx using channel 3 with request 1
  Rx using channel 2 with request 1
  spi1 {
   compatible = "st,stm32-spi";
   dmas = <&dma1 3 1 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
          <&dma1 2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
   dma-names = "tx", "rx";
  };

offset in the table of channels when mapping to a DMAMUX
for 1st dma instance, offset is 0,
for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
plus the nb of dma channels of the 1st dma instance, etc.

Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.

Memory address alignment requirement for DMA buffers used by the controller.

Memory size alignment requirement for DMA buffers used by the controller.

STM32 DMAMUX controller

The STM32 DMAMUX is a direct memory access multiplexer
capable of supporting independent DMA channels.
DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
  1. channel: the mux channel from 0 to <dma-channels> - 1
  2. slot: the request line Multiplexer ID
  which is device dependent:
      -bit 6-7 : Direction  (see dma.h)
             0x0: MEM to MEM
             0x1: MEM to PERIPH
             0x2: PERIPH to MEM
             0x3: reserved for PERIPH to PERIPH
      -bit 9 : Peripheral Increment Address
             0x0: no address increment between transfers
             0x1: increment address between transfers
      -bit 10 : Memory Increment Address
      -bit 11-12 : Peripheral data size
             0x0: Byte (8 bits)
             0x1: Half-word (16 bits)
             0x2: Word (32 bits)
      -bit 13-14 : Memory data size
      -bit 15: Peripheral Increment Offset Size not USED for DMA V2
             0x0: offset size is linked to the peripheral bus width
             0x1: offset size is fixed to 4 (32-bit alignment)
      -bit 16-17 : Priority level
             0x0: low
             0x1: medium
             0x2: high
             0x3: very high
 example for stm32wb55x
   dmamux1: dmamux@40020800 {
       compatible = "st,stm32-dmamux";
       ...
       dma-channels = <14>;
       dma-generators = <4>;
       dma-requests= <36>;
      };
  for client SPI of stm32wb55x
   spi1: spi@40013000 {
       compatible = "st,stm32-spi";
       dmas = <&dmamux1 11 7 0x20440
                &dmamux1 1 6 0x20480>;
       dma-names = "tx", "rx";
      };

Number of DMAMUX output request channels supported by the controller

Number of DMAMUX Peripheral Request Line inputs supported by the controller
This is not directly the value to program in the DMAREQ_ID of the DMAMUX_CxCR

Max nbr of system wake-up pins.
For example wkup-pins-nb = <8>; on the stm32u5

Number of wake-up GPIO sources to select from for each wake-up pin.
If not specified, that means there is only 1 GPIO source for each
wake-up pin.

For example, each wake-up pin on STM32U5 is associated with
4 wake-up sources, 3 of them correspond to GPIOs.

True if SoC has pull-up/down config register(s) for GPIO ports
that are associated with wake-up pins.

STM32 wake-up pin node.

All nodes using this binding must be named "wkup-pin@[index]"
index starts from 1

Specifies the GPIOs, if any, that are associated with the wake-up pin.

For example, for GPIO PB2 associated with wakeup source 1 on wake-up
event 1 on STM32U5 SoCs:
wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>, <...>;

STM32 USB Type-C / Power Delivery.

The default values were taken from the LL_UCPD_StructInit function defined in the HAL.

Determines the division ratio of a kernel clock pre-scaler
producing UCPD peripheral clock (ucpd_clk). It is recommended
to use the pre-scaler so as to set the ucpd_clk frequency in
the range from 6 to 9 MHz.

Determines the division ratio of a ucpd_clk divider producing
inter-frame gap timer clock (tInterFrameGap).
The division ratio 15 is to apply for Tx clock at the USB PD 2.0
specification nominal value.
Valid range: 2 - 32

Determines the division ratio of a hbit_clk divider producing
tTransitionWindow interval.

half-bit clock (hbit_clk)
Valid range: 1 - 64

Determine if USB-C Dead Battery pull-down's should be
applied to the CC lines.

Divides the kernel clock giving the time quanta clock that is fed to the
CAN core(FDCAN_CKDIV).
Note that the divisor is common to all 'st,stm32-fdcan' instances.
Divide by 1 is the peripherals reset value and remains set unless
this property is configured.

Bosch M_CAN message RAM configuration. The cells in the array have the following format:

<offset std-filter-elements ext-filter-elements rx-fifo0-elements rx-fifo1-elements
rx-buffer-elements tx-event-fifo-elements tx-buffer-elements>

The 'offset' is an address offset of the message RAM where the following elements start
from. This is normally set to 0x0 when using a non-shared message RAM. The remaining cells
specify how many elements are allocated for each filter type/FIFO/buffer.

The Bosch M_CAN IP supports the following elements:
11-bit Filter	 0-128 elements / 0-128 words
29-bit Filter	  0-64 elements / 0-128 words
Rx FIFO 0		    0-64 elements / 0-1152 words
Rx FIFO 1		    0-64 elements / 0-1152 words
Rx Buffers	    0-64 elements / 0-1152 words
Tx Event FIFO	  0-32 elements / 0-64 words
Tx Buffers	    0-32 elements / 0-576 words

Deprecated. This property has been renamed to bitrate-data.

Initial data phase bitrate in bit/s.  If this is unset, the initial data phase bitrate is set
to CONFIG_CAN_DEFAULT_BITRATE_DATA.

Initial data phase sample point in per mille (e.g. 875 equals 87.5%).

If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for
bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other
bitrates.

Deprecated. This property has been renamed to bitrate.

Initial bitrate in bit/s. If this is unset, the initial bitrate is set to
CONFIG_CAN_DEFAULT_BITRATE.

Initial sample point in per mille (e.g. 875 equals 87.5%).

bitrates.

Actively controlled CAN transceiver.

Example:
  transceiver0: can-phy0 {
    compatible = "nxp,tja1040", "can-transceiver-gpio";
    standby-gpios = <gpioa 0 GPIO_ACTIVE_HIGH>;
    max-bitrate = <1000000>;
    #phy-cells = <0>;
  };

  &can0 {

    phys = <&transceiver0>;
  };

Passive CAN transceiver. The child node must be named "can-transceiver".

Example:
  &can0 {

    can-transceiver {
      max-bitrate = <1000000>;
    };
  };

The minimum bitrate supported by the CAN transceiver in bits/s.

The maximum bitrate supported by the CAN transceiver in bits/s.

Size of USB dedicated RAM. STM32 SOC's reference
manual defines USB packet SRAM size.

Some boards use a USB DISCONNECT pin to enable
the pull-up resistor on USB Data Positive signal.

Number of bi-directional endpoints supported by hardware
(including EP0)

Number of IN endpoints supported by hardware
(including EP0 IN)

Number of OUT endpoints supported by hardware
(including EP0 OUT)

Configures USB controllers to work up to a specific speed. Valid arguments are "super-speed", "high-speed", "full-speed" and "low-speed". If this is not passed via DT, USB controllers should use their maximum hardware capability.

This binding is to be used by all the usb transceivers which are built-in
with USB IP

Number of cells in a PHY provider. The meaning those
cells is defined by the binding for the phy node.

Minimum residency duration in microseconds.

How much time the residency in a given idle state must last for state entry
to be worthwhile energywise. It includes the time to enter into this state
and represents the "break-even" time to justify the time and power spent
on the work needed for entering and exiting the state based on how much actual energy
is saved once in the state, compared to choosing the next shallowest state.

Worst case latency in microseconds required to exit the idle state.

Disable system managed device power management for this state. When set,
the power management subsystem will not suspend devices before entering
this state.

Signify that this node should result in a dedicated linker script
memory region in the final executable. The region address and size
is taken from the <reg> property, while the name is the value of
this property.

Set attributes such as read-only or executable for the linker script
memory region. The string set here will be specified in parentheses
after the area name in the linker script.

Signify that this node should result in a dedicated MPU region.
Deprecated in favor of 'zephyr,memory-attr'.

Attribute or set of attributes (bitmask) for the memory region. See
'include/zephyr/dt-bindings/memory-attr/memory-attr.h' for a
comprehensive list with description of possible values.

HSE crystal oscillator bypass
Set to the property to by-pass the oscillator with an external clock.

HSE clock security system enabled
Set the property to enable the clock security system (CSS) for the HSE clock.

If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled,
a clock failure event is sent to timers, and a non-maskable interrupt is generated to
inform the software about the failure, allowing the MCU to perform rescue operations.
See the MCU reference manual for details.

The interaction of CSS and low-power modes is unclear from the documentation.
For at least some devices Zephyr will reconfigure the clocks on resuming from low-power
modes; this will include re-enabling CSS. However it is important that you verify
this for your own hardware.

LSE driving capability, within the range 0 to 3.
0 represents the lowests driving capability, 3
the highest.

LSE crystal oscillator bypass
Set the property to by-pass the oscillator with an external clock.

Clock Recovery System using USB SOF packet reception
Set the property to enable clock recovery of the HSI48 oscillator using
the USB SOF packet reception as a reference.

STM32 Microcontroller Clock Output (MCO)

Used to output a clock signal from the MCU to a GPIO pin.
The selected signal goes through a configurable prescaler before output.

Example:
        &mco1 {
                clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>;
                prescaler = <MCO1_PRE(MCO_PRE_DIV_5)>;
                pinctrl-0 = <&rcc_mco_pa8>;
                pinctrl-names = "default";
                status = "okay";
        };

STM32 family TEMP node for production calibrated sensors with two calibration temperatures.

Analog voltage reference (Vref+) voltage with which
temperature sensor calibration parameters have been
measured

ADC resolution used for measuring calibration data

This is usually equal to the ADC's native resolution.

Most series have a 12-bit ADC, but 14-bit and 16-bit
also exists on e.g., STM32U5 and STM32H7 (16) series.

Device engineering bytes address containing the factory-measured
calibration bandgap voltage (VREFINT_CAL).

VDDA/VREF+ voltage in millivolts applied during manufacturing to determine
the internal bandgap voltage reference VREFINT.

also exists on e.g., STM32U5 and STM32H7 series.

Group of GPIO-controlled LEDs.

Each LED is defined in a child node of the gpio-leds node.

Here is an example which defines three LEDs in the node /leds:

/ {
	leds {
		compatible = "gpio-leds";
		led_0 {
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
		};
		led_1 {
			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
		};
		led_2 {
			gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
		};
	};
};

Above:

- led_0 is pin 1 on gpio0. The LED is on when the pin is low,
  and off when the pin is high.
- led_1 is pin 2 on gpio0. The LED is on when the pin is high,
  and off when it is low.
- led_2 is pin 15 on gpio1. The LED is on when the pin is low,
  and the pin's internal pull-up resistor should be enabled.

Human readable string describing the LED. It can be used by an
application to identify this LED or to retrieve its number/index
(i.e. child node number) on the parent device.

Group of GPIO-bound input keys.

This defines a group of buttons that can generate input events. Each button
is defined in a child node of the gpio-keys node and defines a specific key
code.

#include <zephyr/dt-bindings/input/input-event-codes.h>

/ {
       buttons {
               compatible = "gpio-keys";
               button_0 {
                       gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
                       zephyr,code = <INPUT_KEY_0>;
               };
       };
};

Debouncing interval time in milliseconds.
If not specified defaults to 30.

Do not use interrupts for the key GPIOs, poll the pin periodically at the
specified debounce-interval-ms instead.

Do not try to disconnect the pin on suspend. Can be used if the GPIO
controller does not support the GPIO_DISCONNECTED flag.

QEMU, a generic and open source machine emulator and virtualizer

Antmicro's open source simulation and virtual development framework

Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.)

Virtual I/O Device Specification, developed by the OASIS consortium

A stand-in for a real vendor which can be used in examples and tests