added buzzy board to firmware
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273
firmware/boards/iten/buzzy/buzzy.dts
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273
firmware/boards/iten/buzzy/buzzy.dts
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/dts-v1/;
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#include <nordic/nrf52840_qiaa.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/adc/nrf-saadc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/regulator/nrf5x.h>
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#include "buzzy-pinctrl.dtsi"
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/ {
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model = "Buzzy";
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compatible = "iten,buzzy";
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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};
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/* SD_MODE pin for MAX98357A power gating */
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dac_pwr: dac-pwr {
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compatible = "regulator-fixed";
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regulator-name = "max98357a-sd-mode";
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enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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/* Simple SW1 setup: internal pull-up on P1.09, active low when pressed. */
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buttons {
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compatible = "gpio-keys";
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sw1: sw1 {
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gpios = <&gpio1 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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// gpios = <&gpio1 9 (GPIO_ACTIVE_LOW)>;
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label = "SW1";
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};
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};
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/*
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* P0.24 is kept as a normal runtime-controlled GPIO (no gpio-hog).
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* The app can drive this pin high/low to use it as external SW1 pull-up source.
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*/
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sw1_ctrl {
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compatible = "gpio-leds";
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sw1_pullup: sw1_pullup {
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gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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label = "SW1_PULLUP_CTRL";
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};
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};
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/*
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* ETA6003 charger status input on P0.13.
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* Note: CHG status is routed through discrete logic (Q1 path), so polarity may
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* need to be inverted in software. If needed, switch to GPIO_ACTIVE_LOW.
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*/
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charger_status {
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compatible = "gpio-keys";
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chg_status: chg_status {
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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label = "ETA6003_CHG_STATUS";
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};
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};
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/*
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* ETA6003 charge-current select (FCHG) on P0.09:
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* - 0V -> 500 mA
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* - 1.8V -> 1 A
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*/
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charger_ctrl {
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compatible = "gpio-leds";
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chg_fast: chg_fast {
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gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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label = "ETA6003_FAST_CHARGE";
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};
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};
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/*
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* VDDH battery voltage measurement via internal VDDHDIV5 input.
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* The SAADC measures VDDH/5; multiply by 5 in software to get the actual VDDH in mV.
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* 3.1V threshold -> SAADC reads ~620 mV.
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*/
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zephyr_user: zephyr,user {
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io-channels = <&adc 0>;
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io-channel-names = "vddh";
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};
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aliases {
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dac-pwr = &dac_pwr;
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sw1 = &sw1;
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sw1-pullup = &sw1_pullup;
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chg-status = &chg_status;
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chg-fast = &chg_fast;
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external-flash = &mx25r64;
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};
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x00000000 DT_SIZE_K(48)>;
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};
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slot0_partition: partition@c000 {
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label = "image-0";
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reg = <0x0000c000 DT_SIZE_K(472)>;
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};
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slot1_partition: partition@82000 {
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label = "image-1";
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reg = <0x00082000 DT_SIZE_K(472)>;
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};
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storage_partition: partition@f8000 {
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label = "storage";
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reg = <0x000f8000 DT_SIZE_K(32)>;
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};
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};
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};
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/* I2S0 is used for audio output; pins are configured in the pinctrl file. */
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&i2s0 {
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status = "okay";
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pinctrl-0 = <&i2s0_default>;
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pinctrl-1 = <&i2s0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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/*
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* External flash over classic SPI (bring-up-first path).
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* Net mapping from hardware:
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* SCLK -> P0.02
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* SI/SIO0-> P0.29
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* SO/SIO1-> P0.30
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* CS -> P0.05
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*/
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&spi3 {
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status = "okay";
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pinctrl-0 = <&spi3_default>;
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pinctrl-1 = <&spi3_sleep>;
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pinctrl-names = "default", "sleep";
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cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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mx25r64: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <8000000>;
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jedec-id = [c2 28 17];
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size = <DT_SIZE_M(8)>;
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has-dpd;
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t-enter-dpd = <10000>;
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t-exit-dpd = <35000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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ext_flash_lfs: partition@0 {
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label = "ext-littlefs";
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reg = <0x00000000 DT_SIZE_M(8)>;
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};
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};
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};
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};
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/*
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* Optional future QSPI variant (keep disabled for now):
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* - Disable &spi3 block above.
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* - Enable &qspi block below.
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* - Keep the same flash partition layout.
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*/
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// &qspi {
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// status = "okay";
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// pinctrl-0 = <&qspi_default>;
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// pinctrl-1 = <&qspi_sleep>;
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// pinctrl-names = "default", "sleep";
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// mx25r64: flash@0 {
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// compatible = "nordic,qspi-nor";
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// reg = <0>;
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// jedec-id = [c2 28 17];
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// size = <DT_SIZE_M(8)>;
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// has-dpd;
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// t-enter-dpd = <10000>;
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// t-exit-dpd = <35000>;
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// /* Net mapping from hardware: *
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// * SCK=P0.02, CSN=P0.05, IO0=P0.29, IO1=P0.30, IO2=P0.31, IO3=P1.13
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// */
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// sck-pin = <2>;
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// csn-pins = <5>;
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// io-pins = <29>, <30>, <31>, <45>;
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// partitions {
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// compatible = "fixed-partitions";
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// #address-cells = <1>;
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// #size-cells = <1>;
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// ext_flash_lfs: partition@0 {
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// label = "ext-littlefs";
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// reg = <0x00000000 DT_SIZE_M(8)>;
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// };
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// };
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// };
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// };
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpiote {
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status = "okay";
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};
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/* DC/DC mode for regulator 1 (core voltage regulator). */
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®1 {
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regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
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};
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/*
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* DC/DC mode for regulator 0 (I/O voltage regulator, VDD).
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* Default output is 1.8V, suitable for on-board peripherals (flash).
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*/
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®0 {
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status = "okay";
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};
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/*
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* Optional gpio-hog variant for external pull-up via R8 from P0.24 to P1.09:
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* - Keep this disabled when you want runtime control over P0.24.
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* - Remove GPIO_PULL_UP from SW1 gpios above (keep only GPIO_ACTIVE_LOW).
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* - Enable the node below to drive P0.24 high from boot.
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*/
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// &gpio0 {
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// sw1_pullup_hog: sw1_pullup_hog {
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// gpio-hog;
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// gpios = <24 GPIO_ACTIVE_HIGH>;
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// output-high;
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// line-name = "SW1_PULLUP_SRC";
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// };
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// };
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/*
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* Battery voltage measurement via internal VDDHDIV5 channel.
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* No external pin needed; VDDH is divided by 5 internally.
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*/
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&adc {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1_6";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 40)>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <NRF_SAADC_VDDHDIV5>;
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};
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};
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/* Use NFC pins as GPIOs. */
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&uicr {
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nfct-pins-as-gpios;
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};
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