/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
#include "buzzy-pinctrl.dtsi"

/ {
	model = "Buzzy";
	compatible = "iten,buzzy";
	
	chosen {
		zephyr,sram = &sram0;
		zephyr,flash = &flash0;
		zephyr,code-partition = &slot0_partition;
		nordic,pm-ext-flash = &mx25r64;
	};
	
	/* SD_MODE pin for MAX98357A power gating */
	dac_pwr: dac-pwr {
		compatible = "regulator-fixed";
		regulator-name = "max98357a-sd-mode";
		enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
	};
	
	/* Simple SW1 setup: internal pull-up on P1.09, active low when pressed. */
	buttons {
		compatible = "gpio-keys";
		sw1: sw1 {
			gpios = <&gpio1 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
			// gpios = <&gpio1 9 (GPIO_ACTIVE_LOW)>;
			label = "SW1";
		};
	};
	
	/*
	* P0.24 is kept as a normal runtime-controlled GPIO (no gpio-hog).
	* The app can drive this pin high/low to use it as external SW1 pull-up source.
	*/
	sw1_ctrl {
		compatible = "gpio-leds";
		sw1_pullup: sw1_pullup {
			gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
			label = "SW1_PULLUP_CTRL";
		};
	};
	
	/*
	* ETA6003 charger status input on P0.13.
	* Note: CHG status is routed through discrete logic (Q1 path), so polarity may
	* need to be inverted in software. If needed, switch to GPIO_ACTIVE_LOW.
	*/
	charger_status {
		compatible = "gpio-keys";
		chg_status: chg_status {
			gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
			label = "ETA6003_CHG_STATUS";
		};
	};
	
	/*
	* ETA6003 charge-current select (FCHG) on P0.09:
	* - 0V  -> 500 mA
	* - 1.8V -> 1 A
	*/
	charger_ctrl {
		compatible = "gpio-leds";
		chg_fast: chg_fast {
			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
			label = "ETA6003_FAST_CHARGE";
		};
	};
	
	/*
	* VDDH battery voltage measurement via internal VDDHDIV5 input.
	* The SAADC measures VDDH/5; multiply by 5 in software to get the actual VDDH in mV.
	* 3.1V threshold -> SAADC reads ~620 mV.
	*/
	zephyr_user: zephyr,user {
		io-channels = <&adc 0>;
		io-channel-names = "vddh";
	};
	
	aliases {
		dac-pwr = &dac_pwr;
		sw1 = &sw1;
		sw1-pullup = &sw1_pullup;
		chg-status = &chg_status;
		chg-fast = &chg_fast;
		external-flash = &mx25r64;
		i2s-audio = &i2s0;
	};
};

&flash0 {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		
		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x00000000 DT_SIZE_K(48)>;
		};
		
		slot0_partition: partition@c000 {
			label = "image-0";
			reg = <0x0000c000 DT_SIZE_K(472)>;
		};
		
		slot1_partition: partition@82000 {
			label = "image-1";
			reg = <0x00082000 DT_SIZE_K(472)>;
		};
		
		storage_partition: partition@f8000 {
			label = "storage";
			reg = <0x000f8000 DT_SIZE_K(32)>;
		};
	};
};

/* I2S0 is used for audio output; pins are configured in the pinctrl file. */
&i2s0 {
	status = "okay";
	pinctrl-0 = <&i2s0_default>;
	pinctrl-1 = <&i2s0_sleep>;
	pinctrl-names = "default", "sleep";
};

/*
* External flash over classic SPI (bring-up-first path).
* Net mapping from hardware:
*   SCLK   -> P0.02
*   SI/SIO0-> P0.29
*   SO/SIO1-> P0.30
*   CS     -> P0.05
*/
// &spi3 {
// 	status = "okay";
// 	pinctrl-0 = <&spi3_default>;
// 	pinctrl-1 = <&spi3_sleep>;
// 	pinctrl-names = "default", "sleep";
// 	cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;

// 	mx25r64: flash@0 {
// 		compatible = "jedec,spi-nor";
// 		reg = <0>;
// 		spi-max-frequency = <8000000>;
// 		jedec-id = [c2 28 17];
// 		size = <DT_SIZE_M(64)>;
// 		has-dpd;
// 		t-enter-dpd = <10000>;
// 		t-exit-dpd = <35000>;

// 		partitions {
// 			compatible = "fixed-partitions";
// 			#address-cells = <1>;
// 			#size-cells = <1>;

// 			ext_flash_lfs: partition@0 {
// 				label = "ext-littlefs";
// 				reg = <0x00000000 DT_SIZE_M(8)>;
// 			};
// 		};
// 	};
// };

/*
* Optional future QSPI variant (keep disabled for now):
* - Disable &spi3 block above.
* - Enable &qspi block below.
* - Keep the same flash partition layout.
*/
&qspi {
	status = "okay";
	pinctrl-0 = <&qspi_default>;
	pinctrl-1 = <&qspi_sleep>;
	pinctrl-names = "default", "sleep";
	
	mx25r64: flash@0 {
		compatible = "nordic,qspi-nor";
		reg = <0>;
		sck-frequency = <32000000>;
		jedec-id = [c2 28 17];
		size = <DT_SIZE_M(64)>;
		has-dpd;
		t-enter-dpd = <10000>;
		t-exit-dpd = <35000>;
		
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			
			ext_flash_lfs: partition@0 {
				label = "ext-littlefs";
				reg = <0x00000000 DT_SIZE_M(8)>;
			};
		};
	};
};


&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpiote {
	status = "okay";
};

/* DC/DC mode for regulator 1 (core voltage regulator). */
&reg1 {
	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};

/*
* DC/DC mode for regulator 0 (I/O voltage regulator, VDD).
* Default output is 1.8V, suitable for on-board peripherals (flash).
*/
&reg0 {
	status = "okay";
};

/*
* Optional gpio-hog variant for external pull-up via R8 from P0.24 to P1.09:
* - Keep this disabled when you want runtime control over P0.24.
* - Remove GPIO_PULL_UP from SW1 gpios above (keep only GPIO_ACTIVE_LOW).
* - Enable the node below to drive P0.24 high from boot.
*/
// &gpio0 {
// 	sw1_pullup_hog: sw1_pullup_hog {
// 		gpio-hog;
// 		gpios = <24 GPIO_ACTIVE_HIGH>;
// 		output-high;
// 		line-name = "SW1_PULLUP_SRC";
// 	};
// };

/*
* Battery voltage measurement via internal VDDHDIV5 channel.
* No external pin needed; VDDH is divided by 5 internally.
*/
&adc {
	status = "okay";
	
	#address-cells = <1>;
	#size-cells = <0>;
	
	channel@0 {
		reg = <0>;
		zephyr,gain = "ADC_GAIN_1_6";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 40)>;
		zephyr,resolution = <12>;
		zephyr,input-positive = <NRF_SAADC_VDDHDIV5>;
	};
};

/* Use NFC pins as GPIOs. */
&uicr {
	nfct-pins-as-gpios;
};