sync during ir_recv dev
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This commit is contained in:
2026-02-16 13:39:45 +01:00
parent 6376185622
commit 9c1d19af67

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@@ -44,83 +44,74 @@ static const uint8_t test_msg_bits[] = {
/**
* @brief Generates a simulated IR level (0 or 1) based on current position.
*/
static bool get_sim_level(uint32_t pos)
/**
* @brief Improved simulator that respects bit values for timing.
* 0 -> 8 samples space, 8 samples mark (Total 16)
* 1 -> 16 samples space, 8 samples mark (Total 24)
*/
static bool get_sim_level_dynamic(uint32_t *pos)
{
if (pos < 32)
return 1; // Header
if (pos < 40)
return 0; // Gap
uint32_t p = *pos;
uint32_t bit_idx = (pos - 40) / 16;
if (bit_idx < sizeof(test_msg_bits))
// 1. Header: 32 samples mark
if (p < 32)
return 1;
// 2. Initial Gap: 8 samples space
if (p < 40)
return 0;
uint32_t current_p = 40;
for (int i = 0; i < sizeof(test_msg_bits); i++)
{
bool bit_val = test_msg_bits[bit_idx];
uint32_t phase = (pos - 40) % 16;
uint32_t bit_len = test_msg_bits[i] ? 24 : 16; // 16s/8m vs 8s/8m
uint32_t space_len = test_msg_bits[i] ? 16 : 8;
/* * Simplified Pulse Distance:
* Bit 0: 8 samples space, 8 samples mark
* Bit 1: 16 samples space... wait, our state machine
* needs different widths to distinguish.
*/
if (bit_val == 0)
if (p < current_p + bit_len)
{
return (phase >= 8); // 8 samples gap
}
else
{
// For a '1', we need a longer gap in the next sim update
return (phase >= 8);
uint32_t phase = p - current_p;
return (phase >= space_len); // Space first, then Mark
}
current_p += bit_len;
}
return 0;
return 0; // End of message
}
void ir_recv_sim_thread(void *arg1, void *arg2, void *arg3)
{
bool simulation_running = true;
// Update total samples for the new dynamic timing
uint32_t total_samples = 40;
for (int i = 0; i < sizeof(test_msg_bits); i++)
total_samples += (test_msg_bits[i] ? 24 : 16);
// Calculate total expected samples: Header(32) + Gap(8) + Bits(24 * 16)
uint32_t total_expected_samples = 32 + 8 + (sizeof(test_msg_bits) * 16);
while (simulation_running)
while (1)
{
k_usleep(75 * SAMPLES_PER_BUFFER);
int16_t *buf = adc_buffers[write_idx];
for (int i = 0; i < SAMPLES_PER_BUFFER; i++)
{
if (sim_sample_pos >= total_expected_samples)
if (sim_sample_pos < total_samples)
{
simulation_running = false;
// Fill remaining buffer with idle (0)
buf[i * ADC_CHANNELS + 0] = 0;
}
else
{
bool level = get_sim_level(sim_sample_pos);
bool level = get_sim_level_dynamic(&sim_sample_pos);
bool active = IS_ENABLED(CONFIG_IR_RECV_INVERT_SIGNAL) ? !level : level;
buf[i * ADC_CHANNELS + 0] = active ? 0x0FFF : 0x0000;
sim_sample_pos++;
}
// Fill other channels
else
{
buf[i * ADC_CHANNELS + 0] = 0;
if (sim_sample_pos == total_samples)
{
LOG_INF("Simulation sequence finished. Stopping feeder.");
sim_sample_pos++; // Only log once
}
}
buf[i * ADC_CHANNELS + 1] = 0;
buf[i * ADC_CHANNELS + 2] = 0;
buf[i * ADC_CHANNELS + 3] = 2400;
}
write_idx = (write_idx + 1) % BUFFER_COUNT;
k_sem_give(&adc_sem);
if (!simulation_running)
{
LOG_INF("Simulation sequence finished. Stopping feeder.");
// Thread stays alive but does nothing, or use k_thread_abort(k_current_get());
while (1)
{
k_sleep(K_FOREVER);
}
}
}
}
@@ -257,40 +248,36 @@ static void process_ir_sample(ir_channel_ctx_t *ctx, int16_t raw)
{
ir_packet_t packet;
/* Store the 24 bits into our struct bytes */
/* Extraktion der Bytes aus dem Akkumulator */
/* Byte 0 (älteste Bits), Byte 1 (mittlere), Byte 2 (neueste/CRC) */
packet.data.bytes[0] = (ctx->bit_accumulator >> 16) & 0xFF;
packet.data.bytes[1] = (ctx->bit_accumulator >> 8) & 0xFF;
packet.data.bytes[2] = (ctx->bit_accumulator) & 0xFF;
/* Verify integrity */
/* Berechnung der CRC über die ersten zwei Datenbytes */
uint8_t calc = lastertag_crc8(packet.data.bytes, 2);
if (calc == packet.data.fields.crc)
/* Vergleich mit dem empfangenen dritten Byte (CRC) */
if (calc == packet.data.bytes[2])
{
/* Check type and log accordingly */
LOG_INF("SUCCESS! Valid Frame Received.");
if (packet.data.fields.type == 1)
{ // Heal
LOG_INF("HEAL Received! Healer-ID: %u, Amount: %u",
LOG_INF("Type: HEAL, ID: %u, Amount: %u",
packet.data.fields.heal.healer_id,
packet.data.fields.heal.amount);
}
else
{
LOG_INF("Frame Received! Type: %u, Payload: 0x%04X",
packet.data.fields.type,
packet.data.fields.raw_payload);
}
}
else
{
LOG_WRN("CRC Error! Got 0x%02X, expected 0x%02X (Acc: 0x%06X)",
calc, packet.data.fields.crc, ctx->bit_accumulator);
/* Dies wird aktuell ausgelöst, weil 0xA557 -> 0xFB ergibt, nicht 0x71 */
LOG_WRN("CRC Mismatch! Calculated: 0x%02X, Received: 0x%02X (Acc: 0x%06X)",
calc, packet.data.bytes[2], ctx->bit_accumulator);
}
ctx->state = IR_STATE_IDLE;
break;
}
default:
break;
}