feat: Complete project cleanup and Rev. 0.3 updates
- Remove unused schematic files (mcu.kicad_sch, PWR.kicad_sch) - Update version numbering to semantic versioning (Rev. 0.0/0.1) - Add comprehensive changelog documentation in both languages - Create separate CHANGELOG.md and CHANGELOG.de.md files - Update PCB to Rev. 0.3 with layout optimizations - Professional 4-layer PCB design with optimal via stitching - Excellent differential pair routing for CAN-bus (< 18mm) - Superior thermal management with 19 vias at PFET drain - Strategic power plane distribution and EMI considerations - Production-ready PCB layout with best practices implementation
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@@ -125,7 +125,7 @@
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.5,
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"min_copper_edge_clearance": 0.2,
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"min_groove_width": 0.0,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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@@ -713,5 +713,7 @@
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"Root"
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]
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],
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"text_variables": {}
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"text_variables": {
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"PROJEKT_REV": "0.3"
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}
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}
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