Initial commit with basic project structure and Firebeetle 2 board definition
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boards/espressif/esp32c6_devkitc/doc/index.rst
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boards/espressif/esp32c6_devkitc/doc/index.rst
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.. zephyr:board:: esp32c6_devkitc
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Overview
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********
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ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U),
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a general-purpose module with a 8 MB SPI flash. This board integrates complete Wi-Fi,
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Bluetooth LE, Zigbee, and Thread functions. For more information, check `ESP32-C6-DevKitC`_.
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Hardware
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********
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ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the
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802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security
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features and multiple memory resources for IoT products.
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It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz,
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and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz.
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It has a 320KB ROM, a 512KB SRAM, and works with external flash.
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ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U),
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a general-purpose module with a 8 MB SPI flash.
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Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing.
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Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitC on
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a breadboard.
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ESP32-C6 includes the following features:
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- 32-bit core RISC-V microcontroller with a clock speed of up to 160 MHz
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- 400 KB of internal RAM
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- WiFi 802.11 ax 2.4GHz
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- Fully compatible with IEEE 802.11b/g/n protocol
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- Bluetooth LE: Bluetooth 5.3 certified
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- Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna
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- IEEE 802.15.4 (Zigbee and Thread)
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Digital interfaces:
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- 30x GPIOs (QFN40), or 22x GPIOs (QFN32)
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- 2x UART
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- 1x Low-power (LP) UART
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- 1x General purpose SPI
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- 1x I2C
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- 1x Low-power (LP) I2C
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- 1x I2S
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- 1x Pulse counter
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- 1x USB Serial/JTAG controller
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- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)
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- 1x SDIO 2.0 slave controller
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- LED PWM controller, up to 6 channels
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- 1x Motor control PWM (MCPWM)
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- 1x Remote control peripehral
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- 1x Parallel IO interface (PARLIO)
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- General DMA controller (GDMA), with 3 transmit channels and 3 receive channels
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- Event task matrix (ETM)
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Analog interfaces:
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- 1x 12-bit SAR ADCs, up to 7 channels
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- 1x temperature sensor
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Timers:
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- 1x 52-bit system timer
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- 1x 54-bit general-purpose timers
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- 3x Watchdog timers
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- 1x Analog watchdog timer
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Low Power:
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- Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep
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Security:
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- Secure boot
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- Flash encryption
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- 4-Kbit OTP, up to 1792 bits for users
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- Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash)
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- Random number generator (RNG)
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For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference
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manual at `ESP32-C6 Technical Reference Manual`_.
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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System requirements
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*******************
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Prerequisites
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=============
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Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
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below to retrieve those files.
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.. code-block:: console
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west blobs fetch hal_espressif
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.. note::
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It is recommended running the command above after :file:`west update`.
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Building & Flashing
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*******************
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.. zephyr:board-supported-runners::
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Simple boot
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===========
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The board could be loaded using the single binary image, without 2nd stage bootloader.
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It is the default option when building the application without additional configuration.
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.. note::
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Simple boot does not provide any security features nor OTA updates.
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MCUboot bootloader
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==================
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User may choose to use MCUboot bootloader instead. In that case the bootloader
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must be built (and flashed) at least once.
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There are two options to be used when building an application:
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1. Sysbuild
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2. Manual build
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.. note::
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User can select the MCUboot bootloader by adding the following line
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to the board default configuration file.
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.. code:: cfg
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CONFIG_BOOTLOADER_MCUBOOT=y
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Sysbuild
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========
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The sysbuild makes possible to build and flash all necessary images needed to
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bootstrap the board with the EPS32 SoC.
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To build the sample application using sysbuild use the command:
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.. zephyr-app-commands::
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:tool: west
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:zephyr-app: samples/hello_world
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:board: esp32c6_devkitc/esp32c6/hpcore
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:goals: build
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:west-args: --sysbuild
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:compact:
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By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
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images. But it can be configured to create other kind of images.
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Build directory structure created by sysbuild is different from traditional
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Zephyr build. Output is structured by the domain subdirectories:
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.. code-block::
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build/
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├── hello_world
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│ └── zephyr
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│ ├── zephyr.elf
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│ └── zephyr.bin
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├── mcuboot
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│ └── zephyr
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│ ├── zephyr.elf
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│ └── zephyr.bin
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└── domains.yaml
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.. note::
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With ``--sysbuild`` option the bootloader will be re-build and re-flash
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every time the pristine build is used.
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For more information about the system build please read the :ref:`sysbuild` documentation.
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Manual build
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============
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During the development cycle, it is intended to build & flash as quickly possible.
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For that reason, images can be built one at a time using traditional build.
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The instructions following are relevant for both manual build and sysbuild.
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The only difference is the structure of the build directory.
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.. note::
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Remember that bootloader (MCUboot) needs to be flash at least once.
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Build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32c6_devkitc/esp32c6/hpcore
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:goals: build
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The usual ``flash`` target will work with the ``esp32c6_devkitc`` board
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configuration. Here is an example for the :zephyr:code-sample:`hello_world`
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application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32c6_devkitc/esp32c6/hpcore
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:goals: flash
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Open the serial monitor using the following command:
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.. code-block:: shell
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west espressif monitor
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After the board has automatically reset and booted, you should see the following
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message in the monitor:
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.. code-block:: console
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***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
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Hello World! esp32c6_devkitc/esp32c6/hpcore
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Debugging
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*********
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As with much custom hardware, the ESP32-C6 modules require patches to
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OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
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the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_.
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The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
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``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
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parameter when building.
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Here is an example for building the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32c6_devkitc/esp32c6/hpcore
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:goals: build flash
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:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
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You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32c6_devkitc/esp32c6/hpcore
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:goals: debug
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Low-Power CPU (LP CORE)
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***********************
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The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE).
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The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus
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interface for memory and peripheral access.
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The LP Core is in sleep mode by default. It has two application scenarios:
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- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations.
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- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events.
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For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference
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manual at `ESP32-C6 Technical Reference Manual`_.
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The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding
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the following configuration to the project:
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.. code:: cfg
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CONFIG_ULP_COPROC_ENABLED=y
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See :zephyr:code-sample-category:`lp-core` folder as code reference.
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References
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**********
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.. target-notes::
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.. _`ESP32-C6-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/user_guide.html
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.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf
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.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf
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.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
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